Asynchronous VLSI and Architecture

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Neuromorphic Computing

When we write programs that "learn," it turns out that we do and they don't. -- Alan Perlis

     TrueNorth, 1M neurons
     and 256M synapses
This research studies efficient computation structures that are asynchronous and neurally inspired.

The architecture of modern computer systems is quite different from what we know about the organization of the brain. Most silicon circuits use a global clock to coordinate activities while the brain operates in an asynchronous, event-driven manner. There is a clear separation between memory and computation circuits in conventional computers, while memory and computation appear to be tightly integrated in brains. The fan-out of a compute element in CMOS is small relative to the thousands of connections made by an individual neuron to others. The goal of this research direction is to extract computational principles from neuroscience and apply them to silicon-based computation.

One principle seems to be the notion of sending information only when there is a divergence from expected behavior. To capture this notion, we propose a computation structure known as a Δ-dataflow network. Δ-dataflow networks have filtering built-into their computation structure. They can be used to implement a wide variety of operations in an energy efficient manner, and are suited for implementation on an asynchronous architecture.

Another approach we are investigating is in the realm of spiking computation. The neuromorphic VLSI community has been using asynchronous circuits and address-event representation to build systems that mimic biological neurons. Questions that are of interest include: What are the applications of such systems? How can we compute using a spike-based representation? How do we design scalable neuromorphic systems that are highly energy-efficient? How do biological neurons "compute"?


The Brainstorm project, with
The SyNAPSE project, with


Filipp Akopyan (Ph.D. 2011)
Edward Bingham
Nabil Imam (Ph.D. 2014)
Saber Moradi (Ph.D. ETH Zurich)


Tayyar Rzayev, Saber Moradi, David Albonesi, and Rajit Manohar. DeepRecon: Dynamically Reconfigurable Architecture for Accelerating Deep Neural Networks. Proceedings of the International Joint Conference on Neural Networks (IJCNN), May 2017. (abstract)

Tayyar Rzayev, Saber Moradi, David Albonesi, and Rajit Manohar. Fractured Arithmetic Accelerator for Training Deep Neural Networks. Workshop on Hardware and Algorithms for On-chip Learning, International Conference on Computer-Aided Design (ICCAD), November 2016.

Filipp Akopyan, Jun Sawada, Andrew Cassidy, Rodrigo Alvarez-Icaza, John Arthur, Paul Merolla, N Imam, Yutaka Nakamura, Pallab Datta, Gi-Joon Nam, Brian Taba, Michael Beakes, Bernard Brezzo, Jente Kuang, Rajit Manohar, William Risk, Bryan Jackson, and Dharmendra Modha. TrueNorth: Design and Tool Flow of a 65mW 1 Million Neuron Programmable Neurosynaptic Chip. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 34(10), October 2015. (abstract, pdf)   — Keynote paper

Giovanni Rovere, Nabil Imam, Rajit Manohar, and Chiara Bartolozzi. A QDI Asynchronous AER Serializer/Deserializer Link in 180nm for Event-Based Sensors for Robotic Applications. Proceedings of the International Symposium on Circuits and Systems, May 2015. (abstract)

Andrew S. Cassidy, Rodrigo Alvarez-Icaza, Filipp Akopyan, Jun Sawada, John V. Arthur, Paul A. Merolla, Pallab Datta, Marc Gonzalez Tallada, Brian Taba, Alexander Andreopoulos, Arnon Amir, Steven K. Esser, Jeff Kusnitz, Rathinakumar Appuswamy, Chuck Haymes, Bernard Brezzo, Roger Moussalli, Ralph Bellofatto, Christian Baks, Michael Mastro, Kai Schleupen, Charles E. Cox, Ken Inoue, Steve Millman, Nabil Imam, Emmett McQuinn, Yutaka T. Nakamura, Ivan Vo, Chen Guo, Don Nguyen, Scott Lekuch, Sameh Assad, Daniel Friedman, Bryan L. Jackson, Myron D. Flickner, William P. Risk, Rajit Manohar, Dharmendra S. Modha. Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ~100x Speedup in Time-to-Solution and ~100,000x Reduction in Energy-to-Solution. Proceedings of Supercomputing 2014, November 2014. (abstract, pdf)   — ACM Gordon Bell Prize finalist

Paul A. Merolla, John V. Arthur, Rodrigo Alvarez-Icaza, Andrew S. Cassidy, Jun Sawada, Filipp Akopyan, Bryan L. Jackson, Nabil Imam, Chen Guo, Yutaka Nakamura, Bernad Brezzo, Ivan Vo, Steven K. Esser, Rathinakumar Appuswamy, Brian Taba, Arnon Amir, Myron D. Flickner, William P. Risk, Rajit Manohar, and Dharmendra Modha. A Million Spiking-Neuron Integrated Circuit with a Scalable Communication Network and Interface. Science, 345(6197):668--673, August 2014. (abstract, pdf)   — IBM Research 2014 Pat Goldberg Math/CS/EE Best Paper Award

Saber Moradi, Nabil Imam, Rajit Manohar, and Giacomo Indiveri. A Memory-Efficient Routing Method for Large-Scale Spiking Neural Networks. 21st European Conference on Circuit Theory and Design, September 2013. (abstract, pdf)

Nabil Imam, Kyle Wecker, Jonathan Tse, Robert Karmazin, and Rajit Manohar. Neural Spiking Dynamics in Asynchronous Digital Circuits. 2013 International Joint Conference on Neural Networks (IJCNN), August 2013. (abstract, pdf)

Rajit Manohar. Scalable Routing in Large-Scale Neuromorphic Systems. Symposium on Large-Scale Neuromorphic Systems at the Annual International Conference of the IEEE Engineering in Medicine and Biology Society [invited], August 2012.

John Arthur, Paul Merolla, Filipp Akopyan, Rodrigo Alvarez, Andrew Cassidy, Shyamal Chandra, Steven Esser, Nabil Imam, William Risk, Daniel Rubin, Rajit Manohar and Dharmendra Modha. Building Block of a Programmable Neuromorphic Substrate: A Digital Neurosynaptic Core. 2012 International Joint Conference on Neural Networks (IJCNN), June 2012. (abstract, pdf)

Nabil Imam, Thomas Cleland, Rajit Manohar, Paul Merolla, John Arthur, Filipp Akopyan, and Dharmendra Modha. Implementation of Olfactory Bulb Glomerular Layer Computation in a Digital Neurosynaptic Core. Frontiers of Neuromorphic Engineering, Vol. 6, Number 83, June 2012. (abstract, pdf)

Nabil Imam, Filipp Akopyan, Paul Merolla, John Arthur, Rajit Manohar, and Dharmendra Modha. A Digital Neurosynaptic Core Using Event-Driven QDI Circuits. Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2012. (abstract, pdf)   — Best paper award

Paul Merolla, John Arthur, Filipp Akopyan, Nabil Imam, Rajit Manohar, Dharmendra Modha. A Digital Neurosynaptic Core Using Embedded Crossbar Memory with 45pJ per Spike in 45nm. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), September 2011. (abstract, pdf)

Nabil Imam and Rajit Manohar. Address-Event Communication Using Token-Ring Mutual Exclusion. Proceedings of the 17th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), April 2011. (abstract, pdf)

Jon Russo, Mohammed Amduka, Keith Pendersen, Richard Lethin, Jonathan Springer, Rajit Manohar, Rami Melhem. Enabling Cognitive Architectures for UAV Mission Planning. Proceedings of the High Performance Embedded Computing Workshop (HPEC), September 2006. (abstract, pdf)   — Best paper award

Rajit Manohar and K. Mani Chandy. Δ-Dataflow Networks for Event Stream Processing. Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems, November 2004. (abstract, pdf, ps)   — Best paper award