Jakub Szefer
Associate Professor
Department of Electrical Engineering
Yale University
Office Address: 10 Hillhouse Avenue, Dunham Lab, Room 519, New Haven, CT 06511, USA
E-mail: jakub.szefer@yale.edu
PGP Key: pubkey.txt file or from OpenPGP key server

Prospective students interested in Ph.D. study with our group should apply directly to the graduate school and list my name as a potential adviser so I can find the application more easily. Applications are reviewed in early January of each year. Yale undergraduate students please contact me by e-mail.

I run the Computer Architecture and Security Laboratory (CASLAB) at Yale University, where I am fortunate to work with a great group of students. We build architectures and hardware for securing computer systems and cloud cyber-infrastructures.

Our results include novel Secure TLBs and frameworks for security verification of processor caches and whole architectures; hardware accelerators for code-based, hash-based, and lattice-based post-quantum cryptographic (PQC) algorithms on FPGAs (and soon on ASICs); security attacks and defenses for nascent Cloud FPGA computing paradigm and novel side and covert channels in Cloud FPGAs; and DRAM-based Physically Uncloneable Functions. We are also part of the Classic McEliece team in NIST's PQC standardization process.

Our research is supported through current grants: NSF grant 1651945 (DRAM PUFs); NSF grant 1716541 (Hardware Architectures for PQC); NSF grant 1813797 (Security Verification); and NSF grant 1901901 (Cloud FPGA Security). In addition, our research benefits from grants and funding from SRC and TII. We are also thankful for industry donations from Amazon, Xilinx, and Intel (formerly Altera).

I am a Senior Member of the IEEE, a Member of the ACM, and an Associate Member of HiPEAC.

I am a recipient of the 2021 Ackerman Award for Teaching and Mentoring.


Google Scholar: Citations: 2001, H-index: 20 ⬞ DBLPORCID
Citations data was updated on 2021-06-14.

CASLAB publications page has the full list of our publications.

Ilias Giechaskiel, Kasper Rasmussen, and Jakub Szefer, "CAPSULe: Cross-FPGA Covert-Channel Attacks through Power Supply Unit Leakage", in Proceedings of the IEEE Symposium on Security and Privacy (S&P), May 2020.
[ BibTeX

Wenjie Xiong, and Jakub Szefer, "Leaking Information Through Cache LRU States", in Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA), February 2020.
[ BibTeX

Shuwen Deng, Wenjie Xiong, and Jakub Szefer, "Secure TLBs", in Proceedings of the International Symposium on Computer Architecture (ISCA), June 2019.
[ PDF ]  [ BibTeX


I am an author of a first book focusing specifically on design of secure processor architectures, including topics such as Trusted Execution Environments and Side-Channel Threats and Protections.

Jakub Szefer, "Principles of Secure Processor Architecture Design", Morgan & Claypool Publishers, October 2018.

The book's web page can be found here.

For a more fun reading, you can check out a kids book recently published by my mom Ich Troje!


My recent and upcoming seminars or invited talks include:


I regularly give tutorials on processor architectures and security. The most recent (virtual) tutorial was on: Securing Processor Architectures, April 15, 2021, as part of ASPLOS 2021.

The full list of tutorials and free PDFs of the slides are available here.

I have also taught as part of the summer school on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, in July 14-20, 2019, in Fiuggi, Italy, where I gave lectures on Processor Architecture Security.


I am a general co-chair of the new IEEE International Symposium on Secure and Private Execution Environment Design (SEED) which will be held virtually in Sept. 2021.

Each year I am a co-organizer of the workshop on Hardware and Architectural Support for Security and Privacy (HASP). The next workshop is planned to be in October 2021 -- in conjunction with MICRO 2021.

I was a co-organizer of the New England Hardware Security Day 2021 which occured virtually on April 9, 2021.

I was publications chair for FCCM 2021.

I am program committee member (PC) or external review committee (ERC) member of recent and upcoming conferences: TIICS 2021, HPCA 2021, ASPLOS 2021, ISCA 2021 (ERC), HOST 2021, SPSL 2021, MICRO 2021.

Most recently I have served as session chair at following conferences and workshops: Top Picks in Hardware and Embedded Security 2020 Session Two: Side-Channel Attacks on Machine Learning Hardware, HPCA 2021 Session 1A: Security Architectures, ASPLOS 2021 Session 18: Security 1.


I regularly participate in various professional development activities. My recent or upcoming activities include: participating in the "Breaking the Habit of Bias" workshop, Jan. 28, 2021, participating in the Poorvu Center Learning Community: Teaching Science and Labs, Feb. to May, 2021.


EENG 428 / ENAS 968: Cloud FPGA -- In Fall 2019 I will teach first-of-a-kind FPGA course focusing on the new Cloud FPGA computing paradigm. Tentative upcoming fall 2019 course page is here.

EENG 201: Introduction to Computer Engineering -- Every spring, I teach the introductory course for Computer Engineering. Prior spring 2019 course page is here.

EENG 467 / ENAS 967: Computer Organization and Architecture -- I have also taught the intermediate computer architecture course (the first Hennessy and Patterson book). Prior fall 2017 course page is here (I was on a child-rearing leave in fall 2018).


My group regularly publishes hardware (and associated software) code for our projects under open-source licenses, mostly GPLv2 or newer.

To-date my group has published 16 projects totaling 179,056 lines of code. The hardware and software codes can be obtained from CASLAB's code page.
Data was updated on 2020-11-16. The data was computed using this script.

© Jakub Szefer, 2021