ECE 474: Fall 2001

ECE 474 is the introductory digital VLSI course at Cornell. Students in this class have had no prior exposure to VLSI design, and have varied backgrounds (CS, ECE/devices, ECE/circuits, ECE/architecture). The course is designed for advanced juniors and seniors, although it usually also has a few first year graduate students enrolled.

Catalog entry. Introduction to digital VLSI design. Topics include basic transistor physics, switching networks and transistors, combinational and sequential logic, latches, clocking strategies, domino logic, PLAs, memories, physical design, floorplanning, CMOS scaling, performance and power considerations, etc. Lecture and homework topics will emphasize disciplined design, and include CMOS logic, layout, and timing; computer-aided design and analysis tools; and electrical and performance considerations. Students will tape out a small project that will be tested in the following semester.

Fall 2001 Projects. All projects were fabricated in AMI's 0.5 micron process (run T21R) available through MOSIS. The project dimensions are 5000 by 5000 lambda, with lambda=0.3 micron. The stuff in the corner (poly/m1/m2 sandwich) and the large patches of poly were added to satisfy the CMP rules for this process. The pad frame we used allows a layout area of 3600 by 3600 lambda for the project.

Design tools:

magic for VLSI layout (version 7.1)
irsim for digital simulation (version 9.4.1+local mods)
peg for fsm generation
mpla with our own tiles for PLA generation
CAST (local) for circuit description
prs2sim (local) to simulate circuit description with irsim
lvs (local) for physical layout validation
aspice (local) for circuit simulation
wellcheck (local) to check every well is plugged

	Tic Tac Toe Victor Aprea, Paul Grzymkowski, Andre Kozaczka Size: 6584 fets Test results: works
	RISC Processor Eric Chan, Rob Cronin, Matt Stone Size: 9740 fets Test results: parts did not work.
	Atmel-based Processor Tyson Bergland, Andrew Davis, John Tennant Size: 14843 fets Test results: parts did not work.
	MMX Media Processor Andy Chan, Kin Tak Chen, Solomon Chung, Jonathan Klamkin Size: 8650 fets Test results: all instructions worked except jump register.
	MIPS Processor Ross Fleming, Peter Korolov, Aditya Rao Size: 6100 fets Test results: parts did not work.
	Integrated ethernet packet monitor Philip Choi, Patric Lowe, Beckett Madden-Woods Size: 6203 fets Test results: fully functional.
	Programmable FIR Filter Derek Brader, Seth Burnell, Ballard Smith Size: 13520 fets Test results: parts did not work.
	Stack Machine Chris LaFrieda, Jeff Puchalski, Aarif Shaikh Size: 5375 fets Test results: fully functional.
	The Monitor of Power Sriram Chandrasekar, Christopher Foster, Bala Iyer, Carlo Soracco Size: 2865 fets Test results: parts did not work.
	Enigma Machine Chris Chau, Bradley Kopek, Peter Smith Size: 7550 fets Test results: partially working.
	RISC Processor David Biermann, Clint Kelly, Jim Psota Size: 9461 fets Test results: parts did not work
	16-bit RISC Processor David Chao, Bowei Du, Andrew Rae Size: 12680 fets Test results: fully functional
	Data Monitor Ed Cabic, Chirag Fifadra, Fong Yeung Size: 5702 fets Test results: parts did not work.
	Stack processor Eugene Lin, Dimitar Kocoski, Anand Pappu Size: 7800 fets Test results: fully functional.
	2-stage RISC Processor Zain Cheng, Christopher Kung, Ka Fung Lam Size: 10434 fets Test results: fully functional, except load/store instructions calculate the address differently from the original ISA, but consistent with the schematic.
	RSISC Desmond Lee, Gregory Peng, Brian Tarricone Size: 5230 fets Test results: all instructions work except store word.
	IP Firewall Krishna Maheshwari, Gaurav Shukla, David Vitek Size: 5382 fets Test results: fully functional.
	Media Processor Sang Kim, Jenu Rhee, Jeffrey Ting Size: 8902 fets Test results: all instructions work except store word.
	Vector SRAM Adam Clifford, Levy Lorenzo, Tadahiro Kaburaki, Gregory Michalopoulos Size: 10528 fets Test results: parts did not work (wiring problem)
	Vector SRAM Marc Daniels, Yohei Sato, Yabin Wang Size: 13077 fets Test results: control problems; SRAM array functional.
	Direct-mapped Cache Sal Bhimji, Anwar Kashem, Oscar Ramirez Size: 7069 fets Test results: parts did not work.
	Multi-valued Memory Zbigniew Gegala Size: 1398 fets Test results: parts did not work.

Single major reason why a chip did not work: use of edge-triggered flip-flops (without extensive spice-level simulation) instead of two-phase non-overlapping clocking in spite of strong advice to the contrary. :-) They won't do that again. :-)