Design of Tunable Digital Delay Cells

Yu Chen, Rajit Manohar, and Yannis Tsividis

This work discusses design considerations for implementing widely tunable delay cells with good matching properties, low jitter, and robust communication to adjacent circuits. Previously unreported effects that result in signaldependent delay are discussed and eliminated. A 1.2V 65nm CMOS prototype achieves a tunability range from 5ns to 10μs, with a matching standard deviation of 2.3% and a jitter standard deviation of 0.065%.