Cyclone: a static timing and power analysis engine for asynchronous circuits

Wenmian Hua, Yi-Shan Lu, Keshav Pingali, Rajit Manohar

Asynchronous circuits have potential advantages of higher speed and lower power consumption compared to their synchronous counterparts, but their poor CAD support is a major issue limiting adoption. In this paper, we present an integrated timing and power analysis engine capable of handling large asynchronous circuits. For timing, we introduce the notion of performance and correctness slack for asynchronous circuits; for power, we compute both the static and dynamic components. We provide a hierarchical approach to constructing the event-dependency graph, and use the Galois framework for parallelization to achieve fast runtime. The net result is Cyclone, a fast and accurate engine for both static timing and power analysis of asynchronous circuits