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Yihang Yang, Jiayuan He, Rajit Manohar
Asynchronous Very-Large-Scale-Integration (VLSI) has several potential
benefits over its synchronous counterparts, such as reduced power
consumption, elastic pipelining, and robustness to variations.
However, the lack of electronic design automation (EDA) support for
asynchronous circuits, especially physical layout automation tools,
largely limits their adoption. To tackle this challenge, we propose a
gridded cell layout methodology for asynchronous circuits, in which the
cell height and cell width can be any integer multiple of two grid values.
The gridded cell approach combines the shape regularity of standard cells
with the size flexibility of custom design, and thus achieves a better
space utilization ratio and lower wire-length for asynchronous designs.
We present the algorithms and our implementation of Dali, a gridded
cell placer, that consists of an analytical global placer, a
forward-backward legalizer, an N/P-well legalizer, and a power grid router.
We show that the gridded cell placement approach reduces area by 15%
without impacting the routability of the design. We have also used Dali to
tape out a chip in a 65nm process technology, demonstrating that our placer
generates design-rule clean placement.
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