Taking Timing Out of the Equation: Moving Fully Automated Synthesis as close as possible to Delay-Insensitive CircuitsKarthi Srinivasan, Ole Richter, Jordan Schmerge, and Rajit ManoharIn circuit design, delay-insensitivity is regarded as a highly abstract ideal. Delay Insensitive (DI) circuits function correctly independent of specific operating conditions and avoid the need for many technology-specific details. However, their practical application is limited due to the necessity of manual design and the complexity inherent in creating a wide range of circuit features satisfying delay insensitivity. Recent theoretical advancements in the field have led to a re-evaluation of these assumptions. This work aims to address the remaining gaps between theory and practice by proposing an approach to move fully automated design processes as close to integrated DI circuits as possible. The ability to automatically synthesize abstract async Hardware Description Language (HDL) into circuit layout realizations fulfilling the requirements of abstract delay insensitivity for Place and Route (P&R) is enabled by these advancements. This work compares the competitiveness of DI like designs in area and performance to the more common Quasi Delay Insensitive (QDI) and Bundled Data (BD) imple- mentations, discusses the performance overhead in relation to bundled-data designs, and points out the feasibility and cost of delay insensitivity in automated synthesis. |
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