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Virantha Ekanayake and Rajit Manohar
We present the design of a high performance on-chip pipelined asynchronous
DRAM suitable for use in a microprocessor cache. Although traditional DRAM
structures suffer from long access latency and even longer cycle times, our
design achieves a simulated core sub-nanosecond latency and a respectable
cycle time of 4.8ns in a standard 0.25um logic process. We also show how the
cycle time penalty can be overcome by using pipelined interleaved banks with
quasi-delay insensitive asynchronous control circuits. We can thus approach
the performance of SRAM, which is typically used for caches, while still
benefitting from the smaller area footprint of DRAM.
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