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Rui Li, Lincoln Berkley, Yihang Yang, and Rajit Manohar
Current high-level synthesis (HLS) tools that generate
synchronous logic construct a state machine that schedules
program operations in each clock cycle. Rather than this
centralized approach, we are developing an HLS methodology
tailored to high-performance asynchronous dataflow circuits
building on prior work in dataflow synthesis. We propose a
new solution to dataflow circuit generation needed when
translating real-world programs with complex control flow.
We implement our approach in the LLVM compiler framework,
and show that our generated circuits achieve better performance
in throughput and energy compared to a number of existing HLS tools.
We also quantify the benefits of dataflow graph optimizations
on the quality of the generated circuits
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