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Paul Merolla, John Arthur, Filipp Akopyan, Nabil Imam, Rajit Manohar,
Dharmendra Modha
The grand challenge of neuromorphic computation is to develop a flexible
brain-like architecture capable of a wide array of real-time applications,
while striving toward the ultra-low power consumption and compact size of the
human brain---within the constraints of existing silicon and post-silicon
technologies. To this end, we fabricated a key building block of a
modular neuromorphic architecture, a neurosynaptic core, with
256 digital integrate-and-fire neurons and a 1024x256 bit SRAM crossbar
memory for synapses using IBM's 45nm SOI process. Our fully digital
implementation
is able to leverage favorable CMOS scaling trends, while ensuring one-to-one
correspondence between hardware and software. In contrast to a conventional
von Neumann architecture, our core tightly integrates computation (neurons)
alongside memory (synapses), which allows us to implement efficient
fan-out (communication) in a naturally parallel and event-driven manner,
leading to ultra-low active power consumption of 45pJ/spike. The core is fully
configurable in terms of neuron parameters, axon types, and synapse states
and is thus amenable to a wide range of applications. As an example, we
trained a restricted Boltzmann machine offline to perform a visual digital
recognition task, and mapped the learned weights to our chip.
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