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Sandra Jackson and Rajit Manohar
System-on-Chip (SoC) designs using multiple clock
domains are gaining importance due to clock distribution difficulties
and increasing in-die process variations. For the same reasons
more emerging SoC designs utilize clock-less domains for parts
of the system. Both clock domain crossing and clocked/clockless
domain crossing require a mechanism for inter-domain data
transfer that re-synchronizes data to the clock domain of the
receiver and avoids metastability. These synchronizers introduce
added latency and reduce throughput. This paper proposes
merging synchronization with computation in order to reduce
latency while keeping throughput high. The method, called
Gradual Synchronization (GSync), can reduce synchronization
latency at maximum operating frequency by up to 37 percent,
with even greater benefit at slower frequencies. We show the
benefits of this approach in the scenario of an asynchronous
NoC with synchronous end-points.
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