An Energy-Proportional, High-Speed Serial LinkAlex Huang, Amirmohammad Nazari, Robert Soulé, and Rajit ManoharSeveral recent projects have proposed approaches to traffic engineering that schedule workloads to maximize the idle time of network equipment in order to reduce overall power consumption. However, today's switches and network interface cards (NICs) consume significant power even while idle. This power inefficiency both increases operational costs and has a tremendous environmental impact. The key obstacle in realizing an energy proportional switch is physical link performance, i.e., creating a high-speed SERDES (serialization/deserialization) link. Asynchronous circuit designs, which do not rely on a global clock, make any digital computation energy proportional by their nature. However, asynchronous SERDES design is a relatively unexplored topic. In this paper, we improve on a previous SERDES design to incorporate continuous-time equalization hardware and circuit-level optimizations for the digital processing that takes the data rate to 20 Gbps in a 65nm technology. Through circuit simulation, we demonstrate that the SERDES link is energy proportional. Overall, this is an important step towards designing energy-proportional network switches and NICs. |
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