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Karthi Srinivasan and Rajit Manohar
Synthesis of asynchronous circuits from CHP programs has seen
significant improvements in recent times.
We present several improvements and extensions to the
state-of-the-art synthesis technique in order to further improve
the performance of generated circuits and also provide designers
with more power and flexibility. The proposed modifications
are benchmarked against the baseline with pre-layout SPICE
simulations of generated netlists. Comparison in a 65nm node
show average improvements of 9% in area, 16% in delay and
23% in energy consumption.
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