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Rajit Manohar
Challenges in mapping asynchronous logic to a
flexible substrate include developing a balance between circuitlevel
flexibility, mapping complexity, and logic overhead. We have
developed a reconfigurable dataflow architecture that addresses
these challenges, and have also created the necessary synthesis
flow required to map designs to the architecture. The architecture
exploits some of the unique features of asynchronous logic,
and attains a performance that significantly exceeds previous
asynchronous FPGAs.
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