Alain J. Martin, Andrew Lines, Rajit Manohar, Mika Nyström, Robert
Southworth, Paul Penzes, Uri V. Cummings, and Tak-Kwan Lee
The design of an asynchronous clone of a MIPS R3000 is presented. In 0.6um
CMOS, we expect performance close to 280 MIPS for a power consumption of
7 watts. The paper describes the structure of a high-performance
asynchronous pipeline, in particular precise exceptions, pipelined
caches, arithmetic, and registers, and the circuit techniques
developed to achieve high throughput.