Publications

The documents listed below are included by the contributing authors as a means to ensure timely dissemination of scholarly and technical work on a non-commercial basis. Copyright and all rights therein are maintained by the authors or by other copyright holders, notwithstanding that they have offered their works here electronically. It is understood that all persons viewing this information will adhere to the terms and constraints invoked by each author's copyright.

Programmable Substrates
Cross-cutting Projects
Older Projects
By Date: [click to toggle all]

Nitish Srivastava and Rajit Manohar. Data Dependent Frequency Scaling using Desynchronization. Work-in-progress session, Design Automation Conference, June 2018.

Yu Chen, Xiaoyang Zhang, Yong Lian, Rajit Manohar, Yannis Tsividis. A Continuous-Time Digital IIR Filter with Signal-Derived Timing and Fully Agile Power Consumption. IEEE Journal of Solid-State Circuits, 53(2):418-430, February 2018. (abstract, pdf)

Wenmian Hua and Rajit Manohar. Exact Timing Analysis for Asynchronous Systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37(1):203-216, January 2018. (abstract, pdf)

Saber Moradi, Sunil Bhave, and Rajit Manohar. Energy-efficient Hybrid CMOS-NEMS LIF Neuron Circuit in 28nm CMOS. IEEE Symposium Series on Computational Intelligence, November 2017. (pdf)

Asa Dan, Rajit Manohar, and Yoram Moses. On Using Time Without Clocks via Zigzag Causality. ACM Symposium on Principles of Distributed Computing (PODC), July 2017. (pdf)

Rashid Kaleem, Rajit Manohar, and Keshav Pingali. Dionysus: CPUs as accelerators for FPGAs. Work-in-progress session, Design Automation Conference, June 2017.


By Research Area

Neuromorphic Computing [click to toggle all]

Saber Moradi, Sunil Bhave, and Rajit Manohar. Energy-efficient Hybrid CMOS-NEMS LIF Neuron Circuit in 28nm CMOS. IEEE Symposium Series on Computational Intelligence, November 2017. (pdf)

Tayyar Rzayev, Saber Moradi, David Albonesi, and Rajit Manohar. DeepRecon: Dynamically Reconfigurable Architecture for Accelerating Deep Neural Networks. Proceedings of the International Joint Conference on Neural Networks (IJCNN), May 2017. (abstract, pdf)

Design Methodology and Automation [click to toggle all]

Wenmian Hua and Rajit Manohar. Exact Timing Analysis for Asynchronous Systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37(1):203-216, January 2018. (abstract, pdf)

Asa Dan, Rajit Manohar, and Yoram Moses. On Using Time Without Clocks via Zigzag Causality. ACM Symposium on Principles of Distributed Computing (PODC), July 2017. (pdf)

Rajit Manohar and Yoram Moses. The Eventual C-Element Theorem for Delay-Insensitive Asynchronous Circuits. Proceedings of the IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2017. (abstract, pdf)   — Best paper finalist

Nitish Srivastava, Steve Dai, Rajit Manohar, and Zhiru Zhang. Accelerating Face Detection on Programmable SoC Using C-Based Synthesis. Proc. ACM Symposium on Field-Programmable Gate Arrays (FPGA), February 2017. (abstract, pdf)

Energy-efficient VLSI and Arithmetic [click to toggle all]

Nitish Srivastava and Rajit Manohar. Data Dependent Frequency Scaling using Desynchronization. Work-in-progress session, Design Automation Conference, June 2018.

Yu Chen, Xiaoyang Zhang, Yong Lian, Rajit Manohar, Yannis Tsividis. A Continuous-Time Digital IIR Filter with Signal-Derived Timing and Fully Agile Power Consumption. IEEE Journal of Solid-State Circuits, 53(2):418-430, February 2018. (abstract, pdf)

Yu Chen, Xiaoyang Zhang, Yong Lian, Rajit Manohar, and Yannis Tsividis. A Continuous-Time Digital IIR Filter with Signal-Derived Timing. 2017 Symposium on VLSI Circuits, June 2017. (abstract, pdf)

Yu Chen, Rajit Manohar, and Yannis Tsividis. Design of Tunable Delay Cells. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), May 2017. (abstract, pdf)

Tayyar Rzayev, David Albonesi, Rajit Manohar, Francois Guimbretiere, and Jaeyeon Kihm. Toolbox for Exploration of Energy-Efficient Event Processors for Human-Computer Interaction. Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2017. (abstract, pdf)

Asynchronous FPGAs [click to toggle all]

Rashid Kaleem, Rajit Manohar, and Keshav Pingali. Dionysus: CPUs as accelerators for FPGAs. Work-in-progress session, Design Automation Conference, June 2017.

Ultra Low Power Embedded Systems [click to toggle all]

Yu Chen, Xiaoyang Zhang, Yong Lian, Rajit Manohar, Yannis Tsividis. A Continuous-Time Digital IIR Filter with Signal-Derived Timing and Fully Agile Power Consumption. IEEE Journal of Solid-State Circuits, 53(2):418-430, February 2018. (abstract, pdf)

Yu Chen, Xiaoyang Zhang, Yong Lian, Rajit Manohar, and Yannis Tsividis. A Continuous-Time Digital IIR Filter with Signal-Derived Timing. 2017 Symposium on VLSI Circuits, June 2017. (abstract, pdf)

Yu Chen, Rajit Manohar, and Yannis Tsividis. Design of Tunable Delay Cells. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), May 2017. (abstract, pdf)

Asynchronous Computer Architecture [click to toggle all]

Nitish Srivastava and Rajit Manohar. Data Dependent Frequency Scaling using Desynchronization. Work-in-progress session, Design Automation Conference, June 2018.

Tayyar Rzayev, Saber Moradi, David Albonesi, and Rajit Manohar. DeepRecon: Dynamically Reconfigurable Architecture for Accelerating Deep Neural Networks. Proceedings of the International Joint Conference on Neural Networks (IJCNN), May 2017. (abstract, pdf)

Tayyar Rzayev, David Albonesi, Rajit Manohar, Francois Guimbretiere, and Jaeyeon Kihm. Toolbox for Exploration of Energy-Efficient Event Processors for Human-Computer Interaction. Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2017. (abstract, pdf)

Three Dimensional Integration [click to toggle all]

Resilient Asynchronous Systems [click to toggle all]

Selected Technical Reports:

Rajit Manohar. The Impact of Asynchrony on Computer Architecture. Ph.D. thesis, California Institute of Technology, 1998. Available as Caltech technical report CS-TR-98-12 from the Caltech Computer Science department.

Rajit Manohar and Paolo A.G. Sivilotti. Composing Processes Using Modified Rely-Guarantee Specifications. Caltech technical report CS-TR-96-22, November 1996.

Rajit Manohar. Folded FIFOs. Caltech technical report CS-TR-95-09, July 1995.

Issued Patents:

Rajit Manohar and Alain J. Martin. Parallel prefix operations in asynchronous processors. US Patent No. 5,999,961, December 1999.

Rajit Manohar, Mika Nyström, and Alain J. Martin. Exception processing in asynchronous processors. US Patent No. 6,301,655, October 2001.

*Alain J. Martin, Andrew Lines, Rajit Manohar, Uri Cummings, Mika Nyström, Pipelined asynchronous processing. US Patent No. 6,381,692, April 2002.

*Alain J. Martin, Andrew Lines, Rajit Manohar, Uri Cummings, Mika Nyström, Pipelined asynchronous processing. US Patent No. 6,658,550, December 2003.

Mika Nyström, Rajit Manohar, and Alain J. Martin. Method and Apparatus for a failure-free synchronizer. US Patent No. 6,609,203, February 2004.

*John Teifel, Rajit Manohar. Programmable Asynchronous Pipeline Arrays. US Patent No. 7,157,934, January 2007.

David Fang, Filipp Akopyan, Rajit Manohar. Self-timed thermally aware circuits and methods of use thereof. US Patent No. 7,411,439, August 2008.

Filipp Akopyan, Alyssa Apsel, Rajit Manohar. Asynchronous Analog-to-Digital converter and method. US Patent No. 7,466,258, December 2008.

*Rajit Manohar, Clinton Kelly IV. Fault Tolerant Asynchronous Circuits. US Patent No. 7,504,851, March 2009.

*Rajit Manohar, Clinton Kelly IV. Fault Tolerant Asynchronous Circuits. US Patent No. 7,505,304, March 2009.

Rajit Manohar, Clinton Kelly IV. Event-synchronization protocol for parallel simulation of large-scale wireless networks. US Patent No. 7,564,809, July 2009.

*Rajit Manohar. Systems and methods for performing automated conversion of representations of synchronous circuit designs to and from representations of asynchronous circuit designs. US Patent No. 7,610,567, October 2009.

*Rajit Manohar. Methods and systems for converting a synchronous circuit fabric into an asynchronous dataflow circuit fabric. US Patent No. 7,614,029, November 2009.

*Rajit Manohar, Gregor Martin, J. Holt. Synchronous to asynchronous logic conversion. US Patent No. 7,739,628, June 2010.

*Rajit Manohar, Clinton Kelly IV. Fault tolerant asynchronous circuits. US Patent No. 7,741,864, June 2010.

*Rajit Manohar, Clinton Kelly IV. Sensor-network processors using event-driven architecture. US Patent No. 7,788,332, August 2010.

*Rajit Manohar and Clinton Kelly, IV. Reconfigurable Logic Fabrics for Integrated Circuits and Systems and Methods for Configuring Reconfigurable Logic Fabrics. US Patent 7,880,499, February 2011.

*Rajit Manohar, Clinton Kelly, IV, Virantha Ekanayake, Christopher LaFrieda, Hong Tam, Ilya Ganusov, Raymond Nijssen, Marcel van der Goot. Asynchronous Conversion Circuitry: Apparatus, Systems, and Methods. US Patent 7,900,078, March 2011.

*Raymond Njissen, Kamal Chaudhary, Rajit Manohar, Christopher LaFrieda, Clinton Kelly IV, Virantha Ekanayake. One Phase Logic. US Patent 7,932,746, April 2011.

*Rajit Manohar, Clinton Kelly IV, Virantha Ekanayake. Asynchronous Circuit Representations of Synchronous Circuit with Asynchronous Inputs. US Patent 7,982,502, July 2011.

*Rajit Manohar, Clinton Kelly IV. Fault Tolerant Asynchronous Circuits. US Patent 8,004,877, August 2011.

*Rajit Manohar, Clinton Kelly, IV, Virantha Ekanayake, Christopher LaFrieda, Hong Tam, Ilya Ganusov, Raymond Nijssen, Marcel van der Goot. Asynchronous Conversion Circuitry: Apparatus, Systems, and Methods. US Patent 8,078,899, December 2011.

*Gael Paul, Denny Scharf, Rajit Manohar. Logic performance in cyclic structures. US Patent 8,104,004, January 2012.

*Raymond Njissen, Kamal Chaudhary, Rajit Manohar, Christopher LaFrieda, Clinton Kelly IV, Virantha Ekanayake. One Phase Logic. US Patent 8,106,683, January 2012.

*Rajit Manohar and Clinton Kelly, IV. Reconfigurable Logic Fabrics for Integrated Circuits and Systems and Methods for Configuring Reconfigurable Logic Fabrics. US Patent 8,125,242, February 2012.

*Rajit Manohar, Clinton Kelly, IV, Virantha Ekanayake, and Gael Paul. Reset mechanism conversion. US Patent 8,161,435, April 2012.

*Rajit Manohar, Ilya Ganusov, Virantha Ekanayake, Kamal Chaudhury, Clinton Kelly, IV. Non-predicated to predicated conversion of asynchronous representations. US Patent 8,191,019, May 2012.

*Rajit Manohar, Clinton Kelly IV. Fault Tolerant Asynchronous Circuits. US Patent 8,222,915, July 2012.

*Virantha Ekanayake, Clinton Kelly, Rajit Manohar, Christopher LaFrieda, Gael Paul, Raymond Nijssen, Marcel van der Goot. Token enhanced asynchronous conversion of synchronous circuits. US Patent 8,234,607, July 2012.

*Rajit Manohar, Gregor Martin, J. Holt. Synchronous to asynchronous logic conversion. US Patent 8,291,358, October 2012.

*Virantha Ekanayake, Clinton Kelly, Rajit Manohar. Programmable crossbar structures in asynchronous systems. US Patent 8,300,635, October 2012.

*Rajit Manohar, Clinton Kelly, Virantha Ekanayake, Gael Paul, Raymond Nijssen, Marcel van der Goot. Multi-clock asynchroous logic circuits. US Patent 8,301,933, October 2012.

*Rajit Manohar. Converting a synchronous circuit design into an asynchronous design. US Patent 8,375,339, February 2013.

*Rajit Manohar, Clinton Kelly IV, Virantha Ekanayake, Gael Paul. Reset mechanism conversion. US Patent 8,443,315, May 2013.

*Rajit Manohar. Automated conversion of synchronous to asynchronous circuit design representations. US Patent 8,453,079, May 2013.

*Raymond Njissen, Kamal Chaudhary, Rajit Manohar, Christopher LaFrieda, Clinton Kelly IV, Virantha Ekanayake. One Phase Logic. US Patent 8,593,176, November 2013.

*Rajit Manohar, Clinton Kelly IV. Reconfigurable logic fabrics for integrated circuits and systems and methods for configuring reconfigurable logic fabrics. US Patent 8,575,959, November 2013.

*Rajit Manohar, Gael Paul, Raymond Nijssen, Marcel van der Goot, Clinton Kelly, Virantha Ekanayake. Asynchronous systems analysis. US Patent 8,661,378, February 2014.

*Rajit Manohar, Clinton Kelly. Reconfigurable logic fabrics for integrated circuits and systems and methods for configuring reconfigurable logic fabrics. US Patent 8,949,759, February 2015.

*Rajit Manohar, Clinton Kelly, Virantha Ekanayake. Asynchronous pipelined interconnect architecture with fanout support. US Patent 8,964,795, February 2015.

* = either licensed or filed by industry

Notes:

These are "scraps of paper" that are part of my research notes. Some of them turn into publications, but they all contain some idea that I thought was worth recording at the time. If you are interested in any of them (some of them have been cited by papers), send me e-mail.


Errata: The paper on "Slack Elasticity" published in the proceedings of the conference on the Mathematics of Program Construction (1998) has an error in the final printed version due to an unfortunate oversight in proof-reading. Corollary 1 should read: If a system satisfies its specification when the slack on channel c is k, and if it is unchanged when the slack on channel c is l (> k), it satisfies its specification when the slack on c is s, for all s satisfying k <= s <= l. An examination of the proof shows that this is the statement being established, so the proof is identical. This statement was the version presented at the conference as well.

 
  
Yale