Publications

The documents listed below are included by the contributing authors as a means to ensure timely dissemination of scholarly and technical work on a non-commercial basis. Copyright and all rights therein are maintained by the authors or by other copyright holders, notwithstanding that they have offered their works here electronically. It is understood that all persons viewing this information will adhere to the terms and constraints invoked by each author's copyright.

Programmable Substrates
Cross-cutting Projects
Older Projects
By Date: [click to toggle all]

Rajit Manohar, Robert Soulé. Buffer sizing problems in networks and asynchronous circuits: similarities and differences. Workshop on Buffer Sizing, Stanford University, December 2019.

Samira Ataei, Yi-Shan Lu, Jiayuan He, Wenmian Hu, Sepideh Maleki, Yihang Yang, Keshav Pingali, Rajit Manohar. Toward a digital flow for asynchronous VLSI systems. Workshop on Open-Source EDA Technology, International Conference on Computer-Aided Design (ICCAD), November 2019.

Samira Ataei, Rajit Manohar. A unified memory compiler for synchronous and asynchronous circuits. Workshop on Open-Source EDA Technology, International Conference on Computer-Aided Design (ICCAD), November 2019.

Jiayuan He, Martin Burtscher, Rajit Manohar, Keshav Pingali. SPRoute: A Scalable Parallel Negotiation-based Global Router. International Conference on Computer-Aided Design (ICCAD), November 2019.

Jiayuan He, Martin Burtscher, Rajit Manohar, Keshav Pingali. SPRoute: A Scalable Parallel Negotiation-based Global Router. Work-in-progress session, Design Automation Conference, June 2019.


By Research Area

Neuromorphic Computing [click to toggle all]

Alexander Neckar, Sam Fok, Ben Benjamin, Terrence C. Stewart, Nick N. Oza, Aaron R. Voelker, Chris Eliasmith, Rajit Manohar, Kwabena Boahen. Braindrop: A Mixed-Signal Neuromorphic Architecture with a Dynamical Systems-Based Programming Model. Proceeedings of the IEEE, 107(1):144--164, January 2019. (abstract, pdf)

Saber Moradi and Rajit Manohar. The Impact of On-chip Communication on Memory Technologies for Neuromorphic Systems. To appear, Journal of Physics D: Applied Physics, 52(1), Special issue on brain-inspired pervasive computing: from materials to neuromorphic architectures/applications, October 2018. (abstract, pdf)

Saber Moradi, Sunil Bhave, and Rajit Manohar. Energy-efficient Hybrid CMOS-NEMS LIF Neuron Circuit in 28nm CMOS. IEEE Symposium Series on Computational Intelligence, November 2017. (abstract, pdf)

Tayyar Rzayev, Saber Moradi, David Albonesi, and Rajit Manohar. DeepRecon: Dynamically Reconfigurable Architecture for Accelerating Deep Neural Networks. Proceedings of the International Joint Conference on Neural Networks (IJCNN), May 2017. (abstract, pdf)

Tayyar Rzayev, Saber Moradi, David Albonesi, and Rajit Manohar. Fractured Arithmetic Accelerator for Training Deep Neural Networks. Workshop on Hardware and Algorithms for On-chip Learning, International Conference on Computer-Aided Design (ICCAD), November 2016.

Design Methodology and Automation [click to toggle all]

Rajit Manohar, Robert Soulé. Buffer sizing problems in networks and asynchronous circuits: similarities and differences. Workshop on Buffer Sizing, Stanford University, December 2019.

Samira Ataei, Yi-Shan Lu, Jiayuan He, Wenmian Hu, Sepideh Maleki, Yihang Yang, Keshav Pingali, Rajit Manohar. Toward a digital flow for asynchronous VLSI systems. Workshop on Open-Source EDA Technology, International Conference on Computer-Aided Design (ICCAD), November 2019.

Samira Ataei, Rajit Manohar. A unified memory compiler for synchronous and asynchronous circuits. Workshop on Open-Source EDA Technology, International Conference on Computer-Aided Design (ICCAD), November 2019.

Jiayuan He, Martin Burtscher, Rajit Manohar, Keshav Pingali. SPRoute: A Scalable Parallel Negotiation-based Global Router. International Conference on Computer-Aided Design (ICCAD), November 2019.

Jiayuan He, Martin Burtscher, Rajit Manohar, Keshav Pingali. SPRoute: A Scalable Parallel Negotiation-based Global Router. Work-in-progress session, Design Automation Conference, June 2019.

Energy-efficient VLSI and Arithmetic [click to toggle all]

Nitish Srivastava and Rajit Manohar. Operation Dependent Frequency Scaling Using Desynchronization. IEEE Transactions on VLSI, 27(4):799--809 , April 2019. (abstract, pdf)

Alexander Neckar, Sam Fok, Ben Benjamin, Terrence C. Stewart, Nick N. Oza, Aaron R. Voelker, Chris Eliasmith, Rajit Manohar, Kwabena Boahen. Braindrop: A Mixed-Signal Neuromorphic Architecture with a Dynamical Systems-Based Programming Model. Proceeedings of the IEEE, 107(1):144--164, January 2019. (abstract, pdf)

Edward Bingham and Rajit Manohar. QDI Constant Time Counters. IEEE Transactions on VLSI, 27(1):83--91 , January 2019. (abstract, pdf)

Nitish Srivastava and Rajit Manohar. Data Dependent Frequency Scaling using Desynchronization. Work-in-progress session, Design Automation Conference, June 2018.

Yu Chen, Xiaoyang Zhang, Yong Lian, Rajit Manohar, Yannis Tsividis. A Continuous-Time Digital IIR Filter with Signal-Derived Timing and Fully Agile Power Consumption. IEEE Journal of Solid-State Circuits, 53(2):418-430, February 2018. (abstract, pdf)

Asynchronous FPGAs [click to toggle all]

Rashid Kaleem, Rajit Manohar, and Keshav Pingali. Dionysus: CPUs as accelerators for FPGAs. Work-in-progress session, Design Automation Conference, June 2017.

Carlos Tadeo Ortega Otero, Jonathan Tse, Robert Karmazin, Benjamin Hill, and Rajit Manohar. Automatic Obfuscated Cell Layout for Trusted Split-Foundry Design. IEEE International Symposium on Hardware-Oriented Security and Trust, May 2015.

Benjamin Hill, Robert Karmazin, Carlos Tadeo Ortega Otero, Jonathan Tse, and Rajit Manohar. A Split-Foundry Asynchronous FPGA. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), September 2013. (abstract, pdf)

Christopher LaFrieda, Benjamin Hill, and Rajit Manohar. An Asynchronous FPGA with Two-Phase Enable-Scaled Routing. Proceedings of the 16th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2010. (abstract, pdf)   — Best paper finalist

S. Ramaswamy, L. Rockett, D. Patel, S. Danziger, R. Manohar, C. Kelly, J. Holt, V. Ekanayake, D. Elftmann. A Radiation Hardened Reconfigurable FPGA. Proceedings of the IEEE Aerospace Conference, March 2009. (abstract, pdf)

Ultra Low Power Embedded Systems [click to toggle all]

Yu Chen, Xiaoyang Zhang, Yong Lian, Rajit Manohar, Yannis Tsividis. A Continuous-Time Digital IIR Filter with Signal-Derived Timing and Fully Agile Power Consumption. IEEE Journal of Solid-State Circuits, 53(2):418-430, February 2018. (abstract, pdf)

Yu Chen, Xiaoyang Zhang, Yong Lian, Rajit Manohar, and Yannis Tsividis. A Continuous-Time Digital IIR Filter with Signal-Derived Timing. 2017 Symposium on VLSI Circuits, June 2017. (abstract, pdf)

Yu Chen, Rajit Manohar, and Yannis Tsividis. Design of Tunable Delay Cells. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), May 2017. (abstract, pdf)

Carlos Tadeo Ortega Otero, Jonathan Tse, and Rajit Manohar. AES Hardware-Software Co-Design in WSN. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2015. (abstract, pdf)

Benjamin Tang, Sunil Bhave, and Rajit Manohar. Low Power Asynchronous VLSI with NEM Relays. Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2014. (abstract, pdf)   — Best paper finalist

Asynchronous Computer Architecture [click to toggle all]

Nitish Srivastava and Rajit Manohar. Operation Dependent Frequency Scaling Using Desynchronization. IEEE Transactions on VLSI, 27(4):799--809 , April 2019. (abstract, pdf)

Edward Bingham and Rajit Manohar. QDI Constant Time Counters. IEEE Transactions on VLSI, 27(1):83--91 , January 2019. (abstract, pdf)

Nitish Srivastava and Rajit Manohar. Data Dependent Frequency Scaling using Desynchronization. Work-in-progress session, Design Automation Conference, June 2018.

Tayyar Rzayev, Saber Moradi, David Albonesi, and Rajit Manohar. DeepRecon: Dynamically Reconfigurable Architecture for Accelerating Deep Neural Networks. Proceedings of the International Joint Conference on Neural Networks (IJCNN), May 2017. (abstract, pdf)

Tayyar Rzayev, David Albonesi, Rajit Manohar, Francois Guimbretiere, and Jaeyeon Kihm. Toolbox for Exploration of Energy-Efficient Event Processors for Human-Computer Interaction. Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2017. (abstract, pdf)

Three Dimensional Integration [click to toggle all]

Jonathan Tse, Benjamin Hill, and Rajit Manohar. A Bit of Analysis on Self-Timed Single-Bit On-Chip Links. Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2013. (abstract, pdf)

T. Robert Harris, Shivam Priyadarshi, Samson Melamed, Carlos Otero, Rajit Manohar, Steven R. Dooley, Nikhil M. Kriplani, W. Rhett Davis, Paul D. Franzon, and Michael B. Steer. A Transient Electrothermal Analysis of Three-Dimensional Integrated Circuits. IEEE Transactions on Components and Packaging Technologies, 2(4):660–667, April 2012. (abstract)

S. Priyadarshi, T. R. Harris, S. Melamed, C. Otero, N. Kriplani, C. E. Christoffersen, R. Manohar, S. R. Dooley, W. R. Davis, P. D. Franzon, and M. B. Steer. Dynamic electrothermal simulation of three dimensional integrated circuits using standard cell macromodels. IET Circuits, Devices, and Systems, 6(1):35–44, January 2012.

Filipp Akopyan, Carlos Tadeo Ortega Otero, David Fang, Sandra Jackson, and Rajit Manohar. Variability in 3-D Integrated Circuits. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), September 2008. (abstract, pdf)

David Fang, Christopher LaFrieda, Song Peng, and Rajit Manohar. A 3-Tier Asynchronous FPGA. Proceedings of the 23rd International VLSI/ULSI Multilevel Interconnection Conference (VMIC), September 2006. (abstract, pdf)

Resilient Asynchronous Systems [click to toggle all]

S. Ramaswamy, L. Rockett, D. Patel, S. Danziger, R. Manohar, C. Kelly, J. Holt, V. Ekanayake, D. Elftmann. A Radiation Hardened Reconfigurable FPGA. Proceedings of the IEEE Aerospace Conference, March 2009. (abstract, pdf)

Christopher LaFrieda, Engin Ipek, Jose Martinez, and Rajit Manohar. Utilizing dynamically coupled cores to form a resilient chip multiprocessor. Proc. International Conference on Dependable Systems and Networks (DSN), June 2007. (abstract, pdf)

Rajit Manohar, Clinton Kelly IV, et al. Development of Reprogrammable Low Power High Density High Speed RADHARD FPGAs. Government Microcircuit Applications and Critical Technology Conference, March 2007.

Rajit Manohar, Clinton Kelly IV, J. Holt, Chris Liu, Leonard Rockett, Dinu Patel, Steven Danzinger. Application of Low Power High Density Gigahertz Speed Commercial FPGA Technology to High Radiation Applications using RADHARD-by-Process Techniques. Proceedings of the 9th Military and Aerospace Programmable Logic Devices International Conference, September 2006.

Song Peng and Rajit Manohar. Yield Enhancement of Asynchronous Logic Circuits through 3-Dimensional Integration Technology. Proceedings of the ACM Great Lakes Symposium on VLSI (GLVLSI), April 2006. (abstract, pdf)

Selected Technical Reports:

Rajit Manohar. The Impact of Asynchrony on Computer Architecture. Ph.D. thesis, California Institute of Technology, 1998. Available as Caltech technical report CS-TR-98-12 from the Caltech Computer Science department.

Rajit Manohar and Paolo A.G. Sivilotti. Composing Processes Using Modified Rely-Guarantee Specifications. Caltech technical report CS-TR-96-22, November 1996.

Rajit Manohar. Folded FIFOs. Caltech technical report CS-TR-95-09, July 1995.

Issued Patents:

US Patent and Trademark Office search

Notes:

These are "scraps of paper" that are part of my research notes. Some of them turn into publications, but they all contain some idea that I thought was worth recording at the time. If you are interested in any of them (some of them have been cited by papers), send me e-mail.


Errata: The paper on "Slack Elasticity" published in the proceedings of the conference on the Mathematics of Program Construction (1998) has an error in the final printed version due to an unfortunate oversight in proof-reading. Corollary 1 should read: If a system satisfies its specification when the slack on channel c is k, and if it is unchanged when the slack on channel c is l (> k), it satisfies its specification when the slack on c is s, for all s satisfying k <= s <= l. An examination of the proof shows that this is the statement being established, so the proof is identical. This statement was the version presented at the conference as well.

 
  
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