Publications

The documents listed below are included by the contributing authors as a means to ensure timely dissemination of scholarly and technical work on a non-commercial basis. Copyright and all rights therein are maintained by the authors or by other copyright holders, notwithstanding that they have offered their works here electronically. It is understood that all persons viewing this information will adhere to the terms and constraints invoked by each author's copyright.

Programmable Substrates
Cross-cutting Projects
Older Projects
By Date: [click to toggle all]

Ruslan Dashkin and Rajit Manohar. General Approach to Asynchronous Circuits Simulation Using Synchronous FPGAs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 41(10):3452--3465 (TCAD), October 2022. (pdf)

Ioannis Karageorgos, Karthik Sriran, Jan Vesely, Michael Wu, Xiayuan Wen, Nick Lindsay, Lenny Kazan, Rajit Manohar, Abhishek Bhattacharjee. HALO: A Flexible and Low Power Processing Fabric for Brain-Computer Interfaces. HotChips 2022: Workshop on High-Performance Chips, August 2022.

Noa Zilberman, Eve M. Schooler, Uri Cummings, Rajit Manohar, Dawn Nafus, Robert Soulé, Rick Taylor. Toward Carbon-Aware Networking. HotCarbon 2022: 1st Workshop on Sustainable Computer Systems Design and Implementation, July 2022.

Alex Fallin, Aarti Kothari, Jiayuan He, Christopher Yanez, Keshav Pingali, Rajit Manohar, Martin Burtscher. A Simple, Fast, and GPU-friendly Steiner-Tree Heuristic. IEEE International Parallel and Distributed Processing Symposium Workshops, May 2022.

Rajit Manohar. Hardware/software co-design for Neuromorphic Systems. Proceedings of the IEEE Custom Integrated Circuits Conference [invited] (CICC), April 2022. (pdf)


By Research Area

Neuroscience and Computing [click to toggle all]

Ioannis Karageorgos, Karthik Sriran, Jan Vesely, Michael Wu, Xiayuan Wen, Nick Lindsay, Lenny Kazan, Rajit Manohar, Abhishek Bhattacharjee. HALO: A Flexible and Low Power Processing Fabric for Brain-Computer Interfaces. HotChips 2022: Workshop on High-Performance Chips, August 2022.

Rajit Manohar. Hardware/software co-design for Neuromorphic Systems. Proceedings of the IEEE Custom Integrated Circuits Conference [invited] (CICC), April 2022. (pdf)

Prafull Purohit and Rajit Manohar. Hierarchical Token Rings for Address-Event Encoding. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), September 2021. (abstract, pdf)

Karthik Sriram, Ioannis Karageorgos, Jan Vesely, Nick Lindsay, Xiayuan Wen, Michael Wu, Marc Powell, David Borton, Rajit Manohar, Abhishek Bhattacharjee. Balancing Specialized Versus Flexible Computation in Brain-Computer Interfaces. IEEE Micro (special issue on Top Picks from Computer Architecture conferences), 2021. (pdf)

Ioannis Karageorgos, Karthik Sriram, Jan Vesely, Michael Wu, Marc Powell, David Borton, Rajit Manohar, and Abhishek Bhattacharjee. Hardware-software co-design for Brain-Computer Interfaces. Proceedings of the IEEE/ACM Symposium on Computer Architecture (ISCA), June 2020. (abstract, pdf)   — IEEE Micro Top Picks

Design Methodology and Automation [click to toggle all]

Ruslan Dashkin and Rajit Manohar. General Approach to Asynchronous Circuits Simulation Using Synchronous FPGAs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 41(10):3452--3465 (TCAD), October 2022. (pdf)

Alex Fallin, Aarti Kothari, Jiayuan He, Christopher Yanez, Keshav Pingali, Rajit Manohar, Martin Burtscher. A Simple, Fast, and GPU-friendly Steiner-Tree Heuristic. IEEE International Parallel and Distributed Processing Symposium Workshops, May 2022.

Jiayuan He, Udit Agarwal, Yihang Yang, Rajit Manohar, Keshav Pingali. SPRoute 2.0: A detailed routability-driven deterministic parallel global router with soft capacity. 27th Asia and South Pacific Design Automation Conference (ASPDAC), January 2022. (pdf)

Jiayuan He, Wenmian Hua, Yi-Shan Lu, Sepideh Maleki, Yihang Yang, Keshav Pingali, and Rajit Manohar. interact: An Interactive Design Environment for Asynchronous Logic. Workshop on Open-Source EDA Technology, International Conference on Computer-Aided Design (WOSET), November 2021. (pdf)

Rui Li, Lincoln Berkley, Yihang Yang, and Rajit Manohar. Fluid: An Asynchronous High-level Synthesis Tool for Complex Program Structures. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), September 2021. (abstract, pdf)   — Best paper finalist

Energy-efficient VLSI and Arithmetic [click to toggle all]

Noa Zilberman, Eve M. Schooler, Uri Cummings, Rajit Manohar, Dawn Nafus, Robert Soulé, Rick Taylor. Toward Carbon-Aware Networking. HotCarbon 2022: 1st Workshop on Sustainable Computer Systems Design and Implementation, July 2022.

Ned Bingham, Rajit Manohar. Self-Timed Adaptive Digit-Serial Addition. IEEE Transactions on VLSI, 27(9):2131--2141 (TVLSI), September 2019. (abstract, pdf)

Nitish Srivastava and Rajit Manohar. Operation Dependent Frequency Scaling Using Desynchronization. IEEE Transactions on VLSI, 27(4):799--809 (TVLSI), April 2019. (abstract, pdf)

Alexander Neckar, Sam Fok, Ben Benjamin, Terrence C. Stewart, Nick N. Oza, Aaron R. Voelker, Chris Eliasmith, Rajit Manohar, Kwabena Boahen. Braindrop: A Mixed-Signal Neuromorphic Architecture with a Dynamical Systems-Based Programming Model. Proceeedings of the IEEE, 107(1):144--164, January 2019. (abstract, pdf)

Ned Bingham and Rajit Manohar. QDI Constant Time Counters. IEEE Transactions on VLSI, 27(1):83--91 (TVLSI), January 2019. (abstract, pdf)

Asynchronous FPGAs [click to toggle all]

Rashid Kaleem, Rajit Manohar, and Keshav Pingali. Dionysus: CPUs as accelerators for FPGAs. Work-in-progress session, Design Automation Conference, June 2017.

Carlos Tadeo Ortega Otero, Jonathan Tse, Robert Karmazin, Benjamin Hill, and Rajit Manohar. Automatic Obfuscated Cell Layout for Trusted Split-Foundry Design. IEEE International Symposium on Hardware-Oriented Security and Trust, May 2015.

Benjamin Hill, Robert Karmazin, Carlos Tadeo Ortega Otero, Jonathan Tse, and Rajit Manohar. A Split-Foundry Asynchronous FPGA. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), September 2013. (abstract, pdf)

Christopher LaFrieda, Benjamin Hill, and Rajit Manohar. An Asynchronous FPGA with Two-Phase Enable-Scaled Routing. Proceedings of the 16th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2010. (abstract, pdf)   — Best paper finalist

S. Ramaswamy, L. Rockett, D. Patel, S. Danziger, R. Manohar, C. Kelly, J. Holt, V. Ekanayake, D. Elftmann. A Radiation Hardened Reconfigurable FPGA. Proceedings of the IEEE Aerospace Conference, March 2009. (abstract, pdf)

Ultra Low Power Embedded Systems [click to toggle all]

Prafull Purohit and Rajit Manohar. Hierarchical Token Rings for Address-Event Encoding. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), September 2021. (abstract, pdf)

Karthik Sriram, Ioannis Karageorgos, Jan Vesely, Nick Lindsay, Xiayuan Wen, Michael Wu, Marc Powell, David Borton, Rajit Manohar, Abhishek Bhattacharjee. Balancing Specialized Versus Flexible Computation in Brain-Computer Interfaces. IEEE Micro (special issue on Top Picks from Computer Architecture conferences), 2021. (pdf)

Ioannis Karageorgos, Karthik Sriram, Jan Vesely, Michael Wu, Marc Powell, David Borton, Rajit Manohar, and Abhishek Bhattacharjee. Hardware-software co-design for Brain-Computer Interfaces. Proceedings of the IEEE/ACM Symposium on Computer Architecture (ISCA), June 2020. (abstract, pdf)   — IEEE Micro Top Picks

Yu Chen, Xiaoyang Zhang, Yong Lian, Rajit Manohar, Yannis Tsividis. A Continuous-Time Digital IIR Filter with Signal-Derived Timing and Fully Agile Power Consumption. IEEE Journal of Solid-State Circuits, 53(2):418-430 (JSSC), February 2018. (abstract, pdf)

Yu Chen, Xiaoyang Zhang, Yong Lian, Rajit Manohar, and Yannis Tsividis. A Continuous-Time Digital IIR Filter with Signal-Derived Timing. 2017 Symposium on VLSI Circuits, June 2017. (abstract, pdf)

Asynchronous Computer Architecture [click to toggle all]

Adam Wolnikowski, Stephen Ibanez, Jonathan Stone, Changhoon Kim, Rajit Manohar, Robert Soulé. Zerializer: Towards Zero-Copy Serialization. 18th Workshop on Hot Topics in Operating Systems (HotOS), May/June 2021. (abstract, pdf)

Karthik Sriram, Ioannis Karageorgos, Jan Vesely, Nick Lindsay, Xiayuan Wen, Michael Wu, Marc Powell, David Borton, Rajit Manohar, Abhishek Bhattacharjee. Balancing Specialized Versus Flexible Computation in Brain-Computer Interfaces. IEEE Micro (special issue on Top Picks from Computer Architecture conferences), 2021. (pdf)

Ioannis Karageorgos, Karthik Sriram, Jan Vesely, Michael Wu, Marc Powell, David Borton, Rajit Manohar, and Abhishek Bhattacharjee. Hardware-software co-design for Brain-Computer Interfaces. Proceedings of the IEEE/ACM Symposium on Computer Architecture (ISCA), June 2020. (abstract, pdf)   — IEEE Micro Top Picks

Ned Bingham, Rajit Manohar. Self-Timed Adaptive Digit-Serial Addition. IEEE Transactions on VLSI, 27(9):2131--2141 (TVLSI), September 2019. (abstract, pdf)

Nitish Srivastava and Rajit Manohar. Operation Dependent Frequency Scaling Using Desynchronization. IEEE Transactions on VLSI, 27(4):799--809 (TVLSI), April 2019. (abstract, pdf)

Three Dimensional Integration [click to toggle all]

Jonathan Tse, Benjamin Hill, and Rajit Manohar. A Bit of Analysis on Self-Timed Single-Bit On-Chip Links. Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2013. (abstract, pdf)

T. Robert Harris, Shivam Priyadarshi, Samson Melamed, Carlos Otero, Rajit Manohar, Steven R. Dooley, Nikhil M. Kriplani, W. Rhett Davis, Paul D. Franzon, and Michael B. Steer. A Transient Electrothermal Analysis of Three-Dimensional Integrated Circuits. IEEE Transactions on Components and Packaging Technologies, 2(4):660–667, April 2012. (abstract)

S. Priyadarshi, T. R. Harris, S. Melamed, C. Otero, N. Kriplani, C. E. Christoffersen, R. Manohar, S. R. Dooley, W. R. Davis, P. D. Franzon, and M. B. Steer. Dynamic electrothermal simulation of three dimensional integrated circuits using standard cell macromodels. IET Circuits, Devices, and Systems, 6(1):35–44, January 2012.

Filipp Akopyan, Carlos Tadeo Ortega Otero, David Fang, Sandra Jackson, and Rajit Manohar. Variability in 3-D Integrated Circuits. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), September 2008. (abstract, pdf)

David Fang, Christopher LaFrieda, Song Peng, and Rajit Manohar. A 3-Tier Asynchronous FPGA. Proceedings of the 23rd International VLSI/ULSI Multilevel Interconnection Conference (VMIC), September 2006. (abstract, pdf)

Resilient Asynchronous Systems [click to toggle all]

S. Ramaswamy, L. Rockett, D. Patel, S. Danziger, R. Manohar, C. Kelly, J. Holt, V. Ekanayake, D. Elftmann. A Radiation Hardened Reconfigurable FPGA. Proceedings of the IEEE Aerospace Conference, March 2009. (abstract, pdf)

Christopher LaFrieda, Engin Ipek, Jose Martinez, and Rajit Manohar. Utilizing dynamically coupled cores to form a resilient chip multiprocessor. Proc. International Conference on Dependable Systems and Networks (DSN), June 2007. (abstract, pdf)

Rajit Manohar, Clinton Kelly IV, et al. Development of Reprogrammable Low Power High Density High Speed RADHARD FPGAs. Government Microcircuit Applications and Critical Technology Conference, March 2007.

Rajit Manohar, Clinton Kelly IV, J. Holt, Chris Liu, Leonard Rockett, Dinu Patel, Steven Danzinger. Application of Low Power High Density Gigahertz Speed Commercial FPGA Technology to High Radiation Applications using RADHARD-by-Process Techniques. Proceedings of the 9th Military and Aerospace Programmable Logic Devices International Conference, September 2006.

Song Peng and Rajit Manohar. Yield Enhancement of Asynchronous Logic Circuits through 3-Dimensional Integration Technology. Proceedings of the ACM Great Lakes Symposium on VLSI (GLVLSI), April 2006. (abstract, pdf)

Selected Technical Reports:

Rajit Manohar. The Impact of Asynchrony on Computer Architecture. Ph.D. thesis, California Institute of Technology, 1998. Available as Caltech technical report CS-TR-98-12 from the Caltech Computer Science department.

Rajit Manohar and Paolo A.G. Sivilotti. Composing Processes Using Modified Rely-Guarantee Specifications. Caltech technical report CS-TR-96-22, November 1996.

Rajit Manohar. Folded FIFOs. Caltech technical report CS-TR-95-09, July 1995.

Issued Patents:

US Patent and Trademark Office search

Notes:

These are "scraps of paper" that are part of my research notes. Some of them turn into publications, but they all contain some idea that I thought was worth recording at the time. If you are interested in any of them (some of them have been cited by papers), send me e-mail.


Errata:
  • The paper on "Slack Elasticity" published in the proceedings of the conference on the Mathematics of Program Construction (1998) has an error in the final printed version due to an unfortunate oversight in proof-reading. Corollary 1 should read: If a system satisfies its specification when the slack on channel c is k, and if it is unchanged when the slack on channel c is l (> k), it satisfies its specification when the slack on c is s, for all s satisfying k <= s <= l. An examination of the proof shows that this is the statement being established, so the proof is identical. This statement was the version presented at the conference as well.
  • The paper on "AMC" published in ASYNC 2019 has an error in Figure 2 in the write completion circuitry. The p-stack should be powered with Vdd, the output is taken from the node between the n-fet and p-fets, and there is an input inverter on the wreq line. (Thanks to Matt Guthaus for pointing this out!)


 
  
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