Rajit Manohar: Publications

Publications

The documents listed below are included by the contributing authors as a means to ensure timely dissemination of scholarly and technical work on a non-commercial basis. Copyright and all rights therein are maintained by the authors or by other copyright holders, notwithstanding that they have offered their works here electronically. It is understood that all persons viewing this information will adhere to the terms and constraints invoked by each author's copyright.

Programmable Substrates

Neuroscience and Computing
Asynchronous FPGAs
Ultra Low Power Embedded Systems
Asynchronous Computer Architecture

Cross-cutting Projects

Design Methodology and Automation
Energy-efficient VLSI

Older Projects

Three Dimensional Integration
Resilient Asynchronous Systems

By Date: [click to toggle all]: Thomas Jagielski, Xiayuan Wen, Matthew Dobre, Rajit Manohar. Integrating Asynchronous Circuits into the Caravel Testing Harness. Workshop on Open-Source EDA Technology (WOSET), November 2024.; Ruslan Dashkin and Rajit Manohar. Mixed-Level Emulation of Asynchronous Circuits on Synchronous FPGAs. To appear, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2024.; Esteban Ramos, Robert Soulé, Peter Alvaro, Pietro Bressana, Edmund Chen, Uri Cummings, Rui Li, James Tsai, and Rajit Manohar. Split gRPC: An Isolation Architecture for RPC Software Stacks. ACM SIGOPS Asia-Pacific Workshop on Systems, July 2024. (abstract, pdf); Raghavendra Pothukuchi, Karthik Sriram, Michal Gerasimiuk, Muhammed Ugur, Rajit Manohar, Anurag Khandelwal, and Abhishek Bhattacharjee. Distributed Brain-Computer Interfacing with a Networked Multi-Accelerator Architecture. IEEE Micro (special issue on Top Picks from Computer Architecture conferences), 2024. (abstract, pdf); Venkata Pavan Sumanth Sikhakollu, Shreesha Sreedhara, Rajit Manohar, Alan Mishchenko, and Jaijeet Roychowdhury. High Quality Circuit-based 3-SAT Mappings for Oscillator Ising Machines. International Conference on Unconventional Computation and Natural Computation, June 2024. (abstract, pdf); Karthi Srinivasan and Rajit Manohar. Maelstrom: A Logic Synthesis Technique for Asynchronous Circuits. International Workshop on Logic Synthesis (poster) (IWLS), June 2024.; Mattia Vezzoli, Lukas Nel, Kshitij Bhardwaj, Rajit Manohar, and Maya Gokhale. Designing an energy-efficient fully-asynchronous deep learning convolution engine. Late breaking results, Design Automation and Test in Europe (DATE), 2024. (abstract, pdf); Xiaoxuan Yang, Zhangyang Wang, X. Sharon Hu, Chris Kim, Shimeng Yu, Miroslav Pajic, Rajit Manohar, Yiran Chen, and Hai Helen Li. Neuro-symbolic computing: advancements and challenges in hardware-software co-design. IEEE Transactions on Circuits and Systems II (TCAS II), 2023. (abstract, pdf); Noa Zilberman, Eve M. Schooler, Uri Cummings, Rajit Manohar, Dawn Nafus, Robert Soulé, and Rick Taylor. Toward Carbon-Aware Networking. ACM SIGENERGY Energy Informatics Review (EIR), October 2023. (abstract, pdf); Rajit Manohar and Yoram Moses. Timed Signaling Processes. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), July 2023. (abstract, pdf) — Best paper award; Xiang Wu and and Rajit Manohar. Verification-driven Design for Asynchronous VLSI. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), July 2023. (abstract, pdf); Karthi Srinivasan, Yoram Moses, and Rajit Manohar. Opportunistic Mutual Exclusion. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), July 2023. (abstract, pdf) — Best paper nominee; Prafull Purohit, Johannes Leugering, and Rajit Manohar. An Efficient Data Structure for Sparse Bit-Vectors with Applications in Neuromorphic Computing. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), July 2023. (abstract, pdf); Karthik Sriram, Raghavendra Pothukuchi, Michal Gerasimuk, Muhammed Ugur, Oliver Ye Rajit Manohar Anurag Khandelwal, and Abhishek Bhattacharjee. SCALO: An Accelerator-Rich Distributed System for Scalable Brain-Computer Interfacing . IEEE/ACM International Symposium on Computer Architecture (ISCA), July 2023. (abstract, pdf) — Best paper award — IEEE Micro Top Picks; Abhishek Bhattacharjee, Rajit Manohar, and Karthik Sriram,. RETROSPECTIVE: Hardware-software co-design for Brain-Computer Interfaces. ISCA@50 Retrospective, June 2023. (pdf) — ISCA-50 25-year retrospective; Karthik Sriram, Ioannis Karageorgos, Xiayuan Wen, Jan Vesely, Nick Lindsay, Michael Wu, Lenny Kazan, Raghavendra Pothukuchi, Rajit Manohar, and Abhishek Bhattacharjee. HALO: A Hardware-Software Co-Designed Processor for Brain-Computer Interfaces. IEEE Micro, Vol. 43, Issue 3, Special issue from the HotChips 2022 conference, 2023. (pdf); Eve Schooler, Rick Taylor, Noa Zilberman, Robert Soulé, Dawn Nafus, Rajit Manohar, and Uri Cummings. A Perspective on Carbon-aware Networking. Internet Architecture Board Workshop on Environmental Impact of Internet Applications and Systems, December 2022. (pdf); Prafull Purohit and Rajit Manohar. Field-programmable encoding for address-event representation. Frontiers in Neuroscience, 16, December 2022. (pdf); Rajit Manohar. xcell: a library characterizer for combinational and state-holding gates. Workshop on Open-Source EDA Technology, International Conference on Computer-Aided Design (WOSET), November 2022. (pdf); Ruslan Dashkin and Rajit Manohar. General Approach to Asynchronous Circuits Simulation Using Synchronous FPGAs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 41(10):3452--3465 (TCAD), October 2022. (pdf); Ioannis Karageorgos, Karthik Sriran, Jan Vesely, Michael Wu, Xiayuan Wen, Nick Lindsay, Lenny Kazan, Rajit Manohar, Abhishek Bhattacharjee. HALO: A Flexible and Low Power Processing Fabric for Brain-Computer Interfaces. HotChips 2022: Workshop on High-Performance Chips, August 2022. (pdf); Noa Zilberman, Eve M. Schooler, Uri Cummings, Rajit Manohar, Dawn Nafus, Robert Soulé, Rick Taylor. Toward Carbon-Aware Networking. HotCarbon 2022: 1st Workshop on Sustainable Computer Systems Design and Implementation, July 2022. (pdf); Alex Fallin, Aarti Kothari, Jiayuan He, Christopher Yanez, Keshav Pingali, Rajit Manohar, Martin Burtscher. A Simple, Fast, and GPU-friendly Steiner-Tree Heuristic. IEEE International Parallel and Distributed Processing Symposium Workshops, May 2022. (pdf); Rajit Manohar. Hardware/software co-design for Neuromorphic Systems. Proceedings of the IEEE Custom Integrated Circuits Conference [invited] (CICC), April 2022. (pdf); Jiayuan He, Udit Agarwal, Yihang Yang, Rajit Manohar, Keshav Pingali. SPRoute 2.0: A detailed routability-driven deterministic parallel global router with soft capacity. 27th Asia and South Pacific Design Automation Conference (ASPDAC), January 2022. (pdf); Jiayuan He, Wenmian Hua, Yi-Shan Lu, Sepideh Maleki, Yihang Yang, Keshav Pingali, and Rajit Manohar. interact: An Interactive Design Environment for Asynchronous Logic. Workshop on Open-Source EDA Technology, International Conference on Computer-Aided Design (WOSET), November 2021. (pdf); Rui Li, Lincoln Berkley, Yihang Yang, and Rajit Manohar. Fluid: An Asynchronous High-level Synthesis Tool for Complex Program Structures. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), September 2021. (abstract, pdf) — Best paper nominee; Prafull Purohit and Rajit Manohar. Hierarchical Token Rings for Address-Event Encoding. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), September 2021. (abstract, pdf); Adam Wolnikowski, Stephen Ibanez, Jonathan Stone, Changhoon Kim, Rajit Manohar, Robert Soulé. Zerializer: Towards Zero-Copy Serialization. 18th Workshop on Hot Topics in Operating Systems (HotOS), May/June 2021. (abstract, pdf); Karthik Sriram, Ioannis Karageorgos, Jan Vesely, Nick Lindsay, Xiayuan Wen, Michael Wu, Marc Powell, David Borton, Rajit Manohar, Abhishek Bhattacharjee. Balancing Specialized Versus Flexible Computation in Brain-Computer Interfaces. IEEE Micro (special issue on Top Picks from Computer Architecture conferences), 2021. (pdf); Samira Ataei, Wenmian Hua, Yihang Yang, Rajit Manohar, Yi-Shan Lu, Jiayuan He, Sepideh Maleki, Keshav Pingali. An Open-Source EDA flow for Asynchronous Logic. IEEE Design & Test (special issue on open-source EDA), April 2021. (abstract, pdf); Ned Bingham and Rajit Manohar. A Systematic Approach for Arbitration Expressions. IEEE Transactions on Circuits and Systems I: Regular Papers, 67:(12):4960--4969 (TCAS), December 2020. (abstract, pdf); Udit Agarwal, Samira Ataei, Jiayuan He, Wenmian Hua, Yi-Shan Lu, Sepideh Maleki, Yihang Yang, Keshav Pingali, Rajit Manohar. A Digital Flow for Asynchronous VLSI Systems: Status Update. Workshop on Open-Source EDA Technology, International Conference on Computer-Aided Design (WOSET), November 2020. (pdf); Jiayuan He, Yihang Yang, Rajit Manohar. A power router for gridded cell placement. Workshop on Open-Source EDA Technology, International Conference on Computer-Aided Design (WOSET), November 2020. (pdf); Yihang Yang, Jiayuan He, Rajit Manohar. Dali: A gridded cell placement flow. IEEE International Conference on Computer-Aided Design (ICCAD), November 2020. (abstract, pdf); Rajit Manohar. Exact Timing Analysis for Asynchronous Circuits with Multiple Periods. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39(10):3134--3138 (TCAD), October 2020. (abstract, pdf); Yi-Shan Lu, Rajit Manohar, Keshav Pingali. Blitz: A Static Timing Analyzer Parallelized Using Operator Formulation. Work-in-progress session, Design Automation Conference, July 2020.; Ioannis Karageorgos, Karthik Sriram, Jan Vesely, Michael Wu, Marc Powell, David Borton, Rajit Manohar, and Abhishek Bhattacharjee. Hardware-software co-design for Brain-Computer Interfaces. Proceedings of the IEEE/ACM Symposium on Computer Architecture (ISCA), June 2020. (abstract, pdf) — IEEE Micro Top Picks; Samira Ataei, Rajit Manohar. Shared staticizer for area-efficient asynchronous circuits. Proceedings of the IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2020. (abstract, pdf); Wenmian Hua, Yi-Shan Lu, Keshav Pingali, Rajit Manohar. Cyclone: a static timing and power analysis engine for asynchronous circuits. Proceedings of the IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2020. (abstract, pdf) — Best paper award; Wenmian Hua, Yi-Shan Lu, Keshav Pingali, Rajit Manohar. Cyclone: a fast static timing analysis engine for asynchronous circuits. ACM Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 2020.; Samira Ataei, Yi-Shan Lu, Jiayuan He, Wenmian Hu, Sepideh Maleki, Yihang Yang, Keshav Pingali, Rajit Manohar. Toward a digital flow for asynchronous VLSI systems. Workshop on Open-Source EDA Technology, International Conference on Computer-Aided Design (WOSET), November 2019. (pdf) — 2nd place, best open-source tool; Samira Ataei, Rajit Manohar. A unified memory compiler for synchronous and asynchronous circuits. Workshop on Open-Source EDA Technology, International Conference on Computer-Aided Design (WOSET), November 2019. (pdf) — 3rd place, best open-source tool; Jiayuan He, Martin Burtscher, Rajit Manohar, Keshav Pingali. SPRoute: A Scalable Parallel Negotiation-based Global Router. International Conference on Computer-Aided Design (ICCAD), November 2019. (abstract, pdf); Ned Bingham, Rajit Manohar. Self-Timed Adaptive Digit-Serial Addition. IEEE Transactions on VLSI, 27(9):2131--2141 (TVLSI), September 2019. (abstract, pdf); Jiayuan He, Martin Burtscher, Rajit Manohar, Keshav Pingali. SPRoute: A Scalable Parallel Negotiation-based Global Router. Work-in-progress session, Design Automation Conference, June 2019.; Rajit Manohar and Yoram Moses. Asynchronous Signalling Processes. Proceedings of the IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2019. (abstract, pdf); Samira Ataei and Rajit Manohar. AMC: An Asynchronous Memory Compiler. Proceedings of the IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2019. (abstract, pdf) — Best paper nominee; Nitish Srivastava and Rajit Manohar. Operation Dependent Frequency Scaling Using Desynchronization. IEEE Transactions on VLSI, 27(4):799--809 (TVLSI), April 2019. (abstract, pdf); Yi-Shan Lu, Wenmian Hua, Rajit Manohar, and Keshav Pingali. ParallelClosure: A Parallel Design Optimizer for Timing Closure. ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 2019.; Rajit Manohar. An Open-Source Design Flow for Asynchronous Circuits. Government Microcircuit Applications and Critical Technology Conference, March 2019. (abstract, pdf); Alexander Neckar, Sam Fok, Ben Benjamin, Terrence C. Stewart, Nick N. Oza, Aaron R. Voelker, Chris Eliasmith, Rajit Manohar, Kwabena Boahen. Braindrop: A Mixed-Signal Neuromorphic Architecture with a Dynamical Systems-Based Programming Model. Proceeedings of the IEEE, 107(1):144--164, January 2019. (abstract, pdf); Ned Bingham and Rajit Manohar. QDI Constant Time Counters. IEEE Transactions on VLSI, 27(1):83--91 (TVLSI), January 2019. (abstract, pdf); Yi-Shan Lu, Samira Ataei, Jiayuan He, Wenmian Hu, Sepideh Maleki, Yihang Yang, Martin Burtscher, Keshav Pingali, Rajit Manohar. Parallel Tools for Asynchronous VLSI Systems. Workshop on Open-Source EDA Technology, International Conference on Computer-Aided Design (WOSET), November 2018. (abstract, pdf); Saber Moradi and Rajit Manohar. The Impact of On-chip Communication on Memory Technologies for Neuromorphic Systems. Journal of Physics D: Applied Physics, 52(1), Special issue on brain-inspired pervasive computing: from materials to neuromorphic architectures/applications, October 2018. (abstract, pdf); Nitish Srivastava and Rajit Manohar. Data Dependent Frequency Scaling using Desynchronization. Work-in-progress session, Design Automation Conference, June 2018.; Yu Chen, Xiaoyang Zhang, Yong Lian, Rajit Manohar, Yannis Tsividis. A Continuous-Time Digital IIR Filter with Signal-Derived Timing and Fully Agile Power Consumption. IEEE Journal of Solid-State Circuits, 53(2):418-430 (JSSC), February 2018. (abstract, pdf); Wenmian Hua and Rajit Manohar. Exact Timing Analysis for Asynchronous Systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37(1):203-216 (TCAD), January 2018. (abstract, pdf); Saber Moradi, Sunil Bhave, and Rajit Manohar. Energy-efficient Hybrid CMOS-NEMS LIF Neuron Circuit in 28nm CMOS. IEEE Symposium Series on Computational Intelligence, November 2017. (abstract, pdf); Asa Dan, Rajit Manohar, and Yoram Moses. On Using Time Without Clocks via Zigzag Causality. ACM Symposium on Principles of Distributed Computing (PODC), July 2017. (abstract, pdf); Rashid Kaleem, Rajit Manohar, and Keshav Pingali. Dionysus: CPUs as accelerators for FPGAs. Work-in-progress session, Design Automation Conference, June 2017.; Yu Chen, Xiaoyang Zhang, Yong Lian, Rajit Manohar, and Yannis Tsividis. A Continuous-Time Digital IIR Filter with Signal-Derived Timing. 2017 Symposium on VLSI Circuits, June 2017. (abstract, pdf); Rajit Manohar and Yoram Moses. The Eventual C-Element Theorem for Delay-Insensitive Asynchronous Circuits. Proceedings of the IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2017. (abstract, pdf) — Best paper nominee; Tayyar Rzayev, Saber Moradi, David Albonesi, and Rajit Manohar. DeepRecon: Dynamically Reconfigurable Architecture for Accelerating Deep Neural Networks. Proceedings of the International Joint Conference on Neural Networks (IJCNN), May 2017. (abstract, pdf); Yu Chen, Rajit Manohar, and Yannis Tsividis. Design of Tunable Delay Cells. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), May 2017. (abstract, pdf); Tayyar Rzayev, David Albonesi, Rajit Manohar, Francois Guimbretiere, and Jaeyeon Kihm. Toolbox for Exploration of Energy-Efficient Event Processors for Human-Computer Interaction. Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2017. (abstract, pdf); Nitish Srivastava, Steve Dai, Rajit Manohar, and Zhiru Zhang. Accelerating Face Detection on Programmable SoC Using C-Based Synthesis. Proc. ACM Symposium on Field-Programmable Gate Arrays (FPGA), February 2017. (abstract, pdf); Tayyar Rzayev, Saber Moradi, David Albonesi, and Rajit Manohar. Fractured Arithmetic Accelerator for Training Deep Neural Networks. Workshop on Hardware and Algorithms for On-chip Learning, International Conference on Computer-Aided Design (ICCAD), November 2016.; Filipp Akopyan, Carlos Tadeo Ortega Otero, and Rajit Manohar. Hybrid Synchronous-Asynchronous Tool Flow for Emerging VLSI Design. IEEE International Workshop on Logic Synthesis (IWLS), June 2016. (abstract, pdf); Wenmian Hua and Rajit Manohar. Exact Timing Analysis for Concurrent Systems. Work-in-progress session, Design Automation Conference, June 2016.; Sandra Jackson and Rajit Manohar. Gradual Synchronization. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2016. (abstract, pdf) — Best paper nominee; Filipp Akopyan, Jun Sawada, Andrew Cassidy, Rodrigo Alvarez-Icaza, John Arthur, Paul Merolla, Nabil Imam, Yutaka Nakamura, Pallab Datta, Gi-Joon Nam, Brian Taba, Michael Beakes, Bernard Brezzo, Jente Kuang, Rajit Manohar, William Risk, Bryan Jackson, and Dharmendra Modha. TrueNorth: Design and Tool Flow of a 65mW 1 Million Neuron Programmable Neurosynaptic Chip. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 34(10) (TCAD), October 2015. (abstract, pdf) — Keynote paper; Rajit Manohar. Comparing Stochastic and Deterministic Computing. IEEE Computer Architecture Letters, 14(2):119--122, July 2015. (abstract, pdf) — Best of Computer Architecture Letters; Stephen Longfield, Brittany Nkounkou, Rajit Manohar, and Ross Tate. Preventing Glitches and Short Circuits in High-Level Self-Timed Chip Specifications. 36th Annual ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), June 2015. (abstract, pdf); Rajit Manohar and Yoram Moses. Analyzing Isochronic Forks with Potential Causality. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2015. (abstract, pdf) — Best paper nominee; Robert Karmazin, Stephen Longfield, Carlos Tadeo Ortega Otero, and Rajit Manohar. Timing Driven Placement for Quasi Delay-Insensitive Circuits. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2015. (abstract, pdf); Carlos Tadeo Ortega Otero, Jonathan Tse, and Rajit Manohar. AES Hardware-Software Co-Design in WSN. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2015. (abstract, pdf); Carlos Tadeo Ortega Otero, Jonathan Tse, Robert Karmazin, Benjamin Hill, and Rajit Manohar. Automatic Obfuscated Cell Layout for Trusted Split-Foundry Design. IEEE International Symposium on Hardware-Oriented Security and Trust, May 2015.; Giovanni Rovere, Nabil Imam, Rajit Manohar, and Chiara Bartolozzi. A QDI Asynchronous AER Serializer/Deserializer Link in 180nm for Event-Based Sensors for Robotic Applications. Proceedings of the International Symposium on Circuits and Systems, May 2015. (abstract, pdf); Andrew S. Cassidy, Rodrigo Alvarez-Icaza, Filipp Akopyan, Jun Sawada, John V. Arthur, Paul A. Merolla, Pallab Datta, Marc Gonzalez Tallada, Brian Taba, Alexander Andreopoulos, Arnon Amir, Steven K. Esser, Jeff Kusnitz, Rathinakumar Appuswamy, Chuck Haymes, Bernard Brezzo, Roger Moussalli, Ralph Bellofatto, Christian Baks, Michael Mastro, Kai Schleupen, Charles E. Cox, Ken Inoue, Steve Millman, Nabil Imam, Emmett McQuinn, Yutaka T. Nakamura, Ivan Vo, Chen Guo, Don Nguyen, Scott Lekuch, Sameh Assad, Daniel Friedman, Bryan L. Jackson, Myron D. Flickner, William P. Risk, Rajit Manohar, Dharmendra S. Modha. Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ~100x Speedup in Time-to-Solution and ~100,000x Reduction in Energy-to-Solution. Proceedings of Supercomputing 2014, November 2014. (abstract, pdf) — ACM Gordon Bell Prize finalist; Stephen Longfield and Rajit Manohar. Removing Concurrency for Rapid Functional Verification. Proceedings of the 2014 International Conference on Computer-Aided Design (ICCAD), November 2014. (abstract, pdf); Paul A. Merolla, John V. Arthur, Rodrigo Alvarez-Icaza, Andrew S. Cassidy, Jun Sawada, Filipp Akopyan, Bryan L. Jackson, Nabil Imam, Chen Guo, Yutaka Nakamura, Bernad Brezzo, Ivan Vo, Steven K. Esser, Rathinakumar Appuswamy, Brian Taba, Arnon Amir, Myron D. Flickner, William P. Risk, Rajit Manohar, and Dharmendra Modha. A Million Spiking-Neuron Integrated Circuit with a Scalable Communication Network and Interface. Science, 345(6197):668--673, August 2014. (abstract, pdf) — IBM Research 2014 Pat Goldberg Math/CS/EE Best Paper Award; Benjamin Tang, Sunil Bhave, and Rajit Manohar. Low Power Asynchronous VLSI with NEM Relays. Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2014. (abstract, pdf) — Best paper nominee; Jaeyeon Kihm, François Guimbretière, Julia Karl, Rajit Manohar. Using Asymmetric Cores to Reduce Power Consumption for Interactive Devices with Bi-Stable Displays. Proceedings of the ACM CHI Conference on Human Factors in Computing Systems (CHI), April 2014. (abstract, pdf); Carlos Tadeo Ortega Otero, Jonathan Tse, Robert Karmazin, Benjamin Hill, Rajit Manohar. ULSNAP: An Ultra-low Power Event-Driven Microcontroller for Sensor Network Nodes. Proceedings of the IEEE International Symposium on Quality Electronic Design, March 2014. (abstract, pdf); François Guimbretière, Shenwei Liu, Han Wang, Rajit Manohar. An Asymmetric Dual-Processor Architecture for Low Power Information Appliances. ACM Transactions on Embedded Computing Systems, 13(4), February 2014. (abstract, pdf); Benjamin Hill, Robert Karmazin, Carlos Tadeo Ortega Otero, Jonathan Tse, and Rajit Manohar. A Split-Foundry Asynchronous FPGA. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), September 2013. (abstract, pdf); Saber Moradi, Nabil Imam, Rajit Manohar, and Giacomo Indiveri. A Memory-Efficient Routing Method for Large-Scale Spiking Neural Networks. 21st European Conference on Circuit Theory and Design, September 2013. (abstract, pdf); Nabil Imam, Kyle Wecker, Jonathan Tse, Robert Karmazin, and Rajit Manohar. Neural Spiking Dynamics in Asynchronous Digital Circuits. 2013 International Joint Conference on Neural Networks (IJCNN), August 2013. (abstract, pdf); Robert Karmazin, Carlos Otero, and Rajit Manohar. CellTK: Automated Layout for Asynchronous Circuits with Nonstandard Cells. Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2013. (abstract, pdf); Stephen Longfield and Rajit Manohar. Inverting Martin Synthesis for Verification. Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2013. (abstract, pdf) — Best paper award; Jonathan Tse, Benjamin Hill, and Rajit Manohar. A Bit of Analysis on Self-Timed Single-Bit On-Chip Links. Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2013. (abstract, pdf); Benjamin Tang, Stephen Longfield, Rajit Manohar, and Sunil Bhave. Low Power ASIC GPS Tracking Loops: Quantifying the Trade-Offs Between Area, Power and Accuracy. Proc. ION GNSS Technical Meeting, September 2012. — Best presentation award; Rajit Manohar. Scalable Routing in Large-Scale Neuromorphic Systems. Symposium on Large-Scale Neuromorphic Systems at the Annual International Conference of the IEEE Engineering in Medicine and Biology Society [invited], August 2012.; John Arthur, Paul Merolla, Filipp Akopyan, Rodrigo Alvarez, Andrew Cassidy, Shyamal Chandra, Steven Esser, Nabil Imam, William Risk, Daniel Rubin, Rajit Manohar and Dharmendra Modha. Building Block of a Programmable Neuromorphic Substrate: A Digital Neurosynaptic Core. 2012 International Joint Conference on Neural Networks (IJCNN), June 2012. (abstract, pdf); Nabil Imam, Thomas Cleland, Rajit Manohar, Paul Merolla, John Arthur, Filipp Akopyan, and Dharmendra Modha. Implementation of Olfactory Bulb Glomerular Layer Computation in a Digital Neurosynaptic Core. Frontiers of Neuromorphic Engineering, Vol. 6, Number 83, June 2012. (abstract, pdf); Benjamin Tang, Stephen Longfield, Sunil Bhave, and Rajit Manohar. A Low Power Asynchronous GPS Baseband Processor. Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2012. (abstract, pdf); Basit Riaz Sheikh and Rajit Manohar. An Asynchronous Floating-Point Multiplier. Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2012. (abstract, pdf); Nabil Imam, Filipp Akopyan, Paul Merolla, John Arthur, Rajit Manohar, and Dharmendra Modha. A Digital Neurosynaptic Core Using Event-Driven QDI Circuits. Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2012. (abstract, pdf) — Best paper award; T. Robert Harris, Shivam Priyadarshi, Samson Melamed, Carlos Otero, Rajit Manohar, Steven R. Dooley, Nikhil M. Kriplani, W. Rhett Davis, Paul D. Franzon, and Michael B. Steer. A Transient Electrothermal Analysis of Three-Dimensional Integrated Circuits. IEEE Transactions on Components and Packaging Technologies, 2(4):660–667, April 2012. (abstract); S. Priyadarshi, T. R. Harris, S. Melamed, C. Otero, N. Kriplani, C. E. Christoffersen, R. Manohar, S. R. Dooley, W. R. Davis, P. D. Franzon, and M. B. Steer. Dynamic electrothermal simulation of three dimensional integrated circuits using standard cell macromodels. IET Circuits, Devices, and Systems, 6(1):35–44, January 2012.; Basit Riaz Sheikh and Rajit Manohar. Energy-efficient Pipeline Templates for High Performance Asynchronous Circuits. ACM Journal on Emerging Technologies in Computer Systems (special issue on asynchrony in system design), 7(4), December 2011. (abstract, pdf); Paul Merolla, John Arthur, Filipp Akopyan, Nabil Imam, Rajit Manohar, Dharmendra Modha. A Digital Neurosynaptic Core Using Embedded Crossbar Memory with 45pJ per Spike in 45nm. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), September 2011. (abstract, pdf); Nabil Imam and Rajit Manohar. Address-Event Communication Using Token-Ring Mutual Exclusion. Proceedings of the 17th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), April 2011. (abstract, pdf); Basit Riaz Sheikh and Rajit Manohar. An Operand-Optimized Asynchronous IEEE 754 Double-precision floating-point adder. Proceedings of the 16th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2010. (abstract, pdf) — Best paper award; Christopher LaFrieda, Benjamin Hill, and Rajit Manohar. An Asynchronous FPGA with Two-Phase Enable-Scaled Routing. Proceedings of the 16th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2010. (abstract, pdf) — Best paper nominee; Carlos Tadeo Ortega Otero, Jonathan Tse, and Rajit Manohar. Static Power Reduction Techniques for Asynchronous Circuits. Proceedings of the 16th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2010. (abstract, pdf); Christopher LaFrieda and Rajit Manohar. Reducing Power Consumption with Relaxed Quasi Delay-Insensitive Circuits. Proceedings of the 15th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2009. (abstract, pdf); S. Ramaswamy, L. Rockett, D. Patel, S. Danziger, R. Manohar, C. Kelly, J. Holt, V. Ekanayake, D. Elftmann. A Radiation Hardened Reconfigurable FPGA. Proceedings of the IEEE Aerospace Conference, March 2009. (abstract, pdf); Filipp Akopyan, Carlos Tadeo Ortega Otero, David Fang, Sandra Jackson, and Rajit Manohar. Variability in 3-D Integrated Circuits. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), September 2008. (abstract, pdf); Christopher LaFrieda, Engin Ipek, Jose Martinez, and Rajit Manohar. Utilizing dynamically coupled cores to form a resilient chip multiprocessor. Proc. International Conference on Dependable Systems and Networks (DSN), June 2007. (abstract, pdf); Rajit Manohar, Clinton Kelly IV, et al. Development of Reprogrammable Low Power High Density High Speed RADHARD FPGAs. Government Microcircuit Applications and Critical Technology Conference, March 2007.; Rajit Manohar. Reconfigurable Asynchronous Logic. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), September 2006. (abstract, pdf); David Fang, Christopher LaFrieda, Song Peng, and Rajit Manohar. A 3-Tier Asynchronous FPGA. Proceedings of the 23rd International VLSI/ULSI Multilevel Interconnection Conference (VMIC), September 2006. (abstract, pdf); Jon Russo, Mohammed Amduka, Keith Pendersen, Richard Lethin, Jonathan Springer, Rajit Manohar, Rami Melhem. Enabling Cognitive Architectures for UAV Mission Planning. Proceedings of the High Performance Embedded Computing Workshop (HPEC), September 2006. (abstract, pdf) — Best paper award; Rajit Manohar, Clinton Kelly IV, J. Holt, Chris Liu, Leonard Rockett, Dinu Patel, Steven Danzinger. Application of Low Power High Density Gigahertz Speed Commercial FPGA Technology to High Radiation Applications using RADHARD-by-Process Techniques. Proceedings of the 9th Military and Aerospace Programmable Logic Devices International Conference, September 2006.; Song Peng and Rajit Manohar. Yield Enhancement of Asynchronous Logic Circuits through 3-Dimensional Integration Technology. Proceedings of the ACM Great Lakes Symposium on VLSI (GLVLSI), April 2006. (abstract, pdf); Song Peng and Rajit Manohar. Self-healing Asynchronous Arrays. Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), March 2006. (abstract, pdf); Filipp Akopyan, Rajit Manohar, and A. Apsel. A level-crossing Flash Asynchronous Analog-to-Digital Converter. Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), March 2006. (abstract, pdf) — Best paper award; David Fang, Filipp Akopyan, and Rajit Manohar. Self-Timed Thermally Aware Circuits. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), March 2006. (abstract, pdf); Song Peng and Rajit Manohar. Efficient Failure Detection in Pipelined Asynchronous Circuits. Proceedings of the IEEE Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), October 2005. (abstract, pdf); Song Peng and Rajit Manohar. Fault Tolerant Asynchronous Adders through Dynamic Self-reconfiguration. Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2005. (abstract, pdf); Yao-Win Hong, Birsen Sirkeci-Mergen, Anna Scaglione, and Rajit Manohar. Dense Sensor Networks are also Energy-efficient: when `more' is `less'. Proceedings of MILCOM 2005, October 2005. (abstract, pdf) — IEEE Fred Ellersick Award for the best unclassified paper at MILCOM; Christianto C. Liu, Jeng-Huei Chen, Rajit Manohar, and Sandip Tiwari. Mapping Multimedia Applications to 3-D System-on-Chip. Proceedings of the 2005 IEEE International Symposium on Circuits and Systems, May 2005.; David Fang, John Teifel, and Rajit Manohar. A High-Performance Asynchronous FPGA: Test Results. 2005 IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), April 2005. (abstract, pdf); Virantha Ekanayake, Clinton Kelly IV, and Rajit Manohar. BitSNAP: Dynamic Significance Compression for a Low Power Sensor Network Asynchronous Processor. Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), March 2005. (abstract, pdf, ps) — Best paper nominee; Song Peng, David Fang, John Teifel, and Rajit Manohar. Automated Synthesis for Asynchronous FPGAs. 13th ACM International Symposium on Field Programmable Gate Arrays (FPGA), February 2005. (abstract, pdf, ps); John Teifel and Rajit Manohar. An Asynchronous Dataflow FPGA Architecture. IEEE Transactions on Computers (special issue on field-programmable logic), November 2004. (abstract, pdf); Rajit Manohar and K. Mani Chandy. Δ-Dataflow Networks for Event Stream Processing. Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems, November 2004. (abstract, pdf, ps) — Best paper award; Virantha Ekanayake, Clinton Kelly IV, and Rajit Manohar. An Ultra-low-power Processor for Sensor Networks. Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2004. (abstract, pdf, ps); David Biermann, Emin Gun Sirer, and Rajit Manohar. A Rate Matching-based Approach to Dynamic Voltage Scaling. Proceedings of the First Watson Conference on the Interaction between Architecture, Circuits, and Compilers, October 2004. (abstract, pdf, ps); Christopher LaFrieda and Rajit Manohar. Robust Fault Detection and Isolation Techniques for Quasi Delay-Insensitive Circuits. Proceedings of the International Conference on Dependable Systems and Networks (DSN), July 2004. (abstract, pdf, ps); David Fang and Rajit Manohar. Non-Uniform Access Asynchronous Register Files. Proceedings of the 10th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), April 2004. (abstract, pdf, ps); John Teifel and Rajit Manohar. Static Tokens: Using Dataflow to Automate Concurrent Pipeline Synthesis. Proceedings of the 10th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), April 2004. (abstract, pdf, ps); John Teifel and Rajit Manohar. Highly Pipelined Asynchronous FPGAs. 12th ACM International Symposium on Field-Programmable Gate Arrays (FPGA), Monterey, CA, February 2004. [Please see abstract]. (abstract, pdf, ps); Clinton Kelly IV and Rajit Manohar. An Event-Synchronization Protocol for Parallel Simulation of Large-Scale Wireless Networks. Seventh IEEE International Symposium on Distributed Simulation and Real Time Applications, October 2003. (abstract, pdf, ps); John Teifel and Rajit Manohar. Programmable Asynchronous Pipeline Arrays. Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL), pp. 345--354, Lisbon, Portugal, September 2003. (abstract, pdf, ps); Clinton Kelly IV, Virantha Ekanayake, and Rajit Manohar. SNAP: A Sensor Network Asynchronous Processor. Proceedings of the 9th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 24--33, Vancouver, BC, May 2003. (abstract, pdf, ps); John Teifel and Rajit Manohar. A High Speed Clockless Serial Link Tranceiver. Proceedings of the 9th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 151--161, Vancouver, BC, May 2003. (abstract, pdf, ps); Virantha Ekanayake and Rajit Manohar. Asynchronous DRAM Design and Synthesis. Proceedings of the 9th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 174--183, Vancouver, BC, May 2003. (abstract, pdf, ps); Rajit Manohar and Anna Scaglione. Power Optimal Routing in Wireless Networks. IEEE International Conference on Communications, pp. 2979--2984, Anchorage, AK, May 2003. (abstract, pdf); John Teifel, David Fang, David Biermann, Clinton Kelly IV, and Rajit Manohar. Energy-Efficient Pipelines. Proceedings of the 8th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 21--31, Manchester, UK, March 2002. (abstract, ps); Rajit Manohar. Scalable Formal Design Methods for Asynchronous VLSI. Proceedings of the 29th ACM SIGPLAN/SIGACT Conference on the Principles of Programming Languages [invited] (POPL), Portland, OR, January 2002.; Rajit Manohar and Clinton Kelly IV. Network on a Chip: Modeling Wireless Networks with Asynchronous VLSI. IEEE Communications Magazine, pp. 149--155, November 2001. (abstract, pdf, ps); Rajit Manohar. Width-Adaptive Data Word Architectures. Proceedings of the 19th Conference on Advanced Research in VLSI (ARVLSI), pp. 112--129, Salt Lake City, Utah, March 2001. (abstract, pdf, ps); Rajit Manohar, Mika Nyström, and Alain J. Martin. Precise Exceptions in Asynchronous Processors. Proceedings of the 19th Conference on Advanced Research in VLSI (ARVLSI), pp. 16--28, Salt Lake City, Utah, March 2001. (abstract, pdf, ps); Rajit Manohar. An Analysis of Reshuffled Handshaking Expansions. Proceedings of the 7th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 96--105, Salt Lake City, Utah, March 2001. (abstract, pdf, ps); Rajit Manohar. A Case for Asynchronous Computer Architecture. Proceedings of the ISCA Workshop on Complexity-Effective Design, June 2000. (abstract, pdf, ps); Rajit Manohar and Mark Heinrich. A Case For Asynchronous Active Memories. ISCA 2000 Solving the Memory Wall Problem Workshop, June 2000. (abstract, ps); Rajit Manohar. The Entropy of Traces in Parallel Computation. IEEE Transactions on Information Theory, 45(5):1606--1608, July 1999. (abstract, pdf, ps); Rajit Manohar, Tak-Kwan Lee, and Alain J. Martin. Projection: A Synthesis Technique for Concurrent Systems. Proceedings of the 5th IEEE International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), pp. 125--134, April 1999. (abstract, pdf, ps); K. Rustan M. Leino and Rajit Manohar. Joining Specification Statements. Theoretical Computer Science, 216:375-394, March 1999. (abstract, ps); Rajit Manohar and José A. Tierno. Asynchronous Parallel Prefix Computation. IEEE Transactions on Computers, Vol. 47, No. 11, 1244-1252, November 1998. (abstract, ps); Rajit Manohar and Alain J. Martin. Slack Elasticity in Concurent Computing . Proceedings of the Fourth International Conference on the Mathematics of Program Construction (MPC), Lecture Notes in Computer Science 1422, pp. 272-285, Springer-Verlag 1998. (abstract, pdf, ps); Alain J. Martin, Andrew Lines, Rajit Manohar, Mika Nyström, Paul Penzes, Robert Southworth, Uri V. Cummings, and Tak-Kwan Lee. The Design of an Asynchronous MIPS R3000 microprocessor. Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI), pp. 164--181, September 1997. (abstract, pdf, ps); Donald Dabdub and Rajit Manohar. Performance and Portability of an Air Quality Model. Parallel Computing, special issue on Regional Weather Models, 23(14):2187--2200, 1997. (abstract, ps); José A. Tierno, Rajit Manohar, and Alain J. Martin. The Energy and Entropy of VLSI Computations. Proceedings of the 2nd IEEE International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), pp. 188--196, March 1996. (abstract, pdf, ps); Rajit Manohar and Alain J. Martin. Quasi-delay-insensitive circuits are Turing-complete. Proceedings of the 2nd IEEE International Symposium on Advanced Research in Asynchronous Circuits and Systems [invited] (ASYNC), March 1996. Available as Caltech technical report CS-TR-95-11, November 1995. (abstract, pdf, ps); Rajit Manohar and K. Rustan M. Leino. Conditional Composition. Formal Aspects of Computing, 7(6):683--703, 1995. (abstract, ps); K. Mani Chandy, Rajit Manohar, Berna L. Massingill, and Daniel I. Meiron. Integrating Task and Data Parallelism with the Group Communication Archetype. Proceedings of the Ninth International Parallel Processing Symposium (IPPS), pp. 724--733, 1995. (abstract, ps)
Neuroscience and Computing [click to toggle all]: Raghavendra Pothukuchi, Karthik Sriram, Michal Gerasimiuk, Muhammed Ugur, Rajit Manohar, Anurag Khandelwal, and Abhishek Bhattacharjee. Distributed Brain-Computer Interfacing with a Networked Multi-Accelerator Architecture. IEEE Micro (special issue on Top Picks from Computer Architecture conferences), 2024. (abstract, pdf); Prafull Purohit, Johannes Leugering, and Rajit Manohar. An Efficient Data Structure for Sparse Bit-Vectors with Applications in Neuromorphic Computing. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), July 2023. (abstract, pdf); Karthik Sriram, Raghavendra Pothukuchi, Michal Gerasimuk, Muhammed Ugur, Oliver Ye Rajit Manohar Anurag Khandelwal, and Abhishek Bhattacharjee. SCALO: An Accelerator-Rich Distributed System for Scalable Brain-Computer Interfacing . IEEE/ACM International Symposium on Computer Architecture (ISCA), July 2023. (abstract, pdf) — Best paper award — IEEE Micro Top Picks; Abhishek Bhattacharjee, Rajit Manohar, and Karthik Sriram,. RETROSPECTIVE: Hardware-software co-design for Brain-Computer Interfaces. ISCA@50 Retrospective, June 2023. (pdf) — ISCA-50 25-year retrospective; Karthik Sriram, Ioannis Karageorgos, Xiayuan Wen, Jan Vesely, Nick Lindsay, Michael Wu, Lenny Kazan, Raghavendra Pothukuchi, Rajit Manohar, and Abhishek Bhattacharjee. HALO: A Hardware-Software Co-Designed Processor for Brain-Computer Interfaces. IEEE Micro, Vol. 43, Issue 3, Special issue from the HotChips 2022 conference, 2023. (pdf); Prafull Purohit and Rajit Manohar. Field-programmable encoding for address-event representation. Frontiers in Neuroscience, 16, December 2022. (pdf); Ioannis Karageorgos, Karthik Sriran, Jan Vesely, Michael Wu, Xiayuan Wen, Nick Lindsay, Lenny Kazan, Rajit Manohar, Abhishek Bhattacharjee. HALO: A Flexible and Low Power Processing Fabric for Brain-Computer Interfaces. HotChips 2022: Workshop on High-Performance Chips, August 2022. (pdf); Rajit Manohar. Hardware/software co-design for Neuromorphic Systems. Proceedings of the IEEE Custom Integrated Circuits Conference [invited] (CICC), April 2022. (pdf); Prafull Purohit and Rajit Manohar. Hierarchical Token Rings for Address-Event Encoding. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), September 2021. (abstract, pdf); Karthik Sriram, Ioannis Karageorgos, Jan Vesely, Nick Lindsay, Xiayuan Wen, Michael Wu, Marc Powell, David Borton, Rajit Manohar, Abhishek Bhattacharjee. Balancing Specialized Versus Flexible Computation in Brain-Computer Interfaces. IEEE Micro (special issue on Top Picks from Computer Architecture conferences), 2021. (pdf); Ioannis Karageorgos, Karthik Sriram, Jan Vesely, Michael Wu, Marc Powell, David Borton, Rajit Manohar, and Abhishek Bhattacharjee. Hardware-software co-design for Brain-Computer Interfaces. Proceedings of the IEEE/ACM Symposium on Computer Architecture (ISCA), June 2020. (abstract, pdf) — IEEE Micro Top Picks; Alexander Neckar, Sam Fok, Ben Benjamin, Terrence C. Stewart, Nick N. Oza, Aaron R. Voelker, Chris Eliasmith, Rajit Manohar, Kwabena Boahen. Braindrop: A Mixed-Signal Neuromorphic Architecture with a Dynamical Systems-Based Programming Model. Proceeedings of the IEEE, 107(1):144--164, January 2019. (abstract, pdf); Saber Moradi and Rajit Manohar. The Impact of On-chip Communication on Memory Technologies for Neuromorphic Systems. Journal of Physics D: Applied Physics, 52(1), Special issue on brain-inspired pervasive computing: from materials to neuromorphic architectures/applications, October 2018. (abstract, pdf); Saber Moradi, Sunil Bhave, and Rajit Manohar. Energy-efficient Hybrid CMOS-NEMS LIF Neuron Circuit in 28nm CMOS. IEEE Symposium Series on Computational Intelligence, November 2017. (abstract, pdf); Tayyar Rzayev, Saber Moradi, David Albonesi, and Rajit Manohar. DeepRecon: Dynamically Reconfigurable Architecture for Accelerating Deep Neural Networks. Proceedings of the International Joint Conference on Neural Networks (IJCNN), May 2017. (abstract, pdf); Tayyar Rzayev, Saber Moradi, David Albonesi, and Rajit Manohar. Fractured Arithmetic Accelerator for Training Deep Neural Networks. Workshop on Hardware and Algorithms for On-chip Learning, International Conference on Computer-Aided Design (ICCAD), November 2016.; Filipp Akopyan, Jun Sawada, Andrew Cassidy, Rodrigo Alvarez-Icaza, John Arthur, Paul Merolla, Nabil Imam, Yutaka Nakamura, Pallab Datta, Gi-Joon Nam, Brian Taba, Michael Beakes, Bernard Brezzo, Jente Kuang, Rajit Manohar, William Risk, Bryan Jackson, and Dharmendra Modha. TrueNorth: Design and Tool Flow of a 65mW 1 Million Neuron Programmable Neurosynaptic Chip. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 34(10) (TCAD), October 2015. (abstract, pdf) — Keynote paper; Giovanni Rovere, Nabil Imam, Rajit Manohar, and Chiara Bartolozzi. A QDI Asynchronous AER Serializer/Deserializer Link in 180nm for Event-Based Sensors for Robotic Applications. Proceedings of the International Symposium on Circuits and Systems, May 2015. (abstract, pdf); Andrew S. Cassidy, Rodrigo Alvarez-Icaza, Filipp Akopyan, Jun Sawada, John V. Arthur, Paul A. Merolla, Pallab Datta, Marc Gonzalez Tallada, Brian Taba, Alexander Andreopoulos, Arnon Amir, Steven K. Esser, Jeff Kusnitz, Rathinakumar Appuswamy, Chuck Haymes, Bernard Brezzo, Roger Moussalli, Ralph Bellofatto, Christian Baks, Michael Mastro, Kai Schleupen, Charles E. Cox, Ken Inoue, Steve Millman, Nabil Imam, Emmett McQuinn, Yutaka T. Nakamura, Ivan Vo, Chen Guo, Don Nguyen, Scott Lekuch, Sameh Assad, Daniel Friedman, Bryan L. Jackson, Myron D. Flickner, William P. Risk, Rajit Manohar, Dharmendra S. Modha. Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ~100x Speedup in Time-to-Solution and ~100,000x Reduction in Energy-to-Solution. Proceedings of Supercomputing 2014, November 2014. (abstract, pdf) — ACM Gordon Bell Prize finalist; Paul A. Merolla, John V. Arthur, Rodrigo Alvarez-Icaza, Andrew S. Cassidy, Jun Sawada, Filipp Akopyan, Bryan L. Jackson, Nabil Imam, Chen Guo, Yutaka Nakamura, Bernad Brezzo, Ivan Vo, Steven K. Esser, Rathinakumar Appuswamy, Brian Taba, Arnon Amir, Myron D. Flickner, William P. Risk, Rajit Manohar, and Dharmendra Modha. A Million Spiking-Neuron Integrated Circuit with a Scalable Communication Network and Interface. Science, 345(6197):668--673, August 2014. (abstract, pdf) — IBM Research 2014 Pat Goldberg Math/CS/EE Best Paper Award; Saber Moradi, Nabil Imam, Rajit Manohar, and Giacomo Indiveri. A Memory-Efficient Routing Method for Large-Scale Spiking Neural Networks. 21st European Conference on Circuit Theory and Design, September 2013. (abstract, pdf); Nabil Imam, Kyle Wecker, Jonathan Tse, Robert Karmazin, and Rajit Manohar. Neural Spiking Dynamics in Asynchronous Digital Circuits. 2013 International Joint Conference on Neural Networks (IJCNN), August 2013. (abstract, pdf); Rajit Manohar. Scalable Routing in Large-Scale Neuromorphic Systems. Symposium on Large-Scale Neuromorphic Systems at the Annual International Conference of the IEEE Engineering in Medicine and Biology Society [invited], August 2012.; John Arthur, Paul Merolla, Filipp Akopyan, Rodrigo Alvarez, Andrew Cassidy, Shyamal Chandra, Steven Esser, Nabil Imam, William Risk, Daniel Rubin, Rajit Manohar and Dharmendra Modha. Building Block of a Programmable Neuromorphic Substrate: A Digital Neurosynaptic Core. 2012 International Joint Conference on Neural Networks (IJCNN), June 2012. (abstract, pdf); Nabil Imam, Thomas Cleland, Rajit Manohar, Paul Merolla, John Arthur, Filipp Akopyan, and Dharmendra Modha. Implementation of Olfactory Bulb Glomerular Layer Computation in a Digital Neurosynaptic Core. Frontiers of Neuromorphic Engineering, Vol. 6, Number 83, June 2012. (abstract, pdf); Nabil Imam, Filipp Akopyan, Paul Merolla, John Arthur, Rajit Manohar, and Dharmendra Modha. A Digital Neurosynaptic Core Using Event-Driven QDI Circuits. Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2012. (abstract, pdf) — Best paper award; Paul Merolla, John Arthur, Filipp Akopyan, Nabil Imam, Rajit Manohar, Dharmendra Modha. A Digital Neurosynaptic Core Using Embedded Crossbar Memory with 45pJ per Spike in 45nm. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), September 2011. (abstract, pdf); Nabil Imam and Rajit Manohar. Address-Event Communication Using Token-Ring Mutual Exclusion. Proceedings of the 17th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), April 2011. (abstract, pdf); Jon Russo, Mohammed Amduka, Keith Pendersen, Richard Lethin, Jonathan Springer, Rajit Manohar, Rami Melhem. Enabling Cognitive Architectures for UAV Mission Planning. Proceedings of the High Performance Embedded Computing Workshop (HPEC), September 2006. (abstract, pdf) — Best paper award; Rajit Manohar and K. Mani Chandy. Δ-Dataflow Networks for Event Stream Processing. Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems, November 2004. (abstract, pdf, ps) — Best paper award
Design Methodology and Automation [click to toggle all]: Thomas Jagielski, Xiayuan Wen, Matthew Dobre, Rajit Manohar. Integrating Asynchronous Circuits into the Caravel Testing Harness. Workshop on Open-Source EDA Technology (WOSET), November 2024.; Ruslan Dashkin and Rajit Manohar. Mixed-Level Emulation of Asynchronous Circuits on Synchronous FPGAs. To appear, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2024.; Karthi Srinivasan and Rajit Manohar. Maelstrom: A Logic Synthesis Technique for Asynchronous Circuits. International Workshop on Logic Synthesis (poster) (IWLS), June 2024.; Rajit Manohar and Yoram Moses. Timed Signaling Processes. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), July 2023. (abstract, pdf) — Best paper award; Xiang Wu and and Rajit Manohar. Verification-driven Design for Asynchronous VLSI. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), July 2023. (abstract, pdf); Karthi Srinivasan, Yoram Moses, and Rajit Manohar. Opportunistic Mutual Exclusion. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), July 2023. (abstract, pdf) — Best paper nominee; Rajit Manohar. xcell: a library characterizer for combinational and state-holding gates. Workshop on Open-Source EDA Technology, International Conference on Computer-Aided Design (WOSET), November 2022. (pdf); Ruslan Dashkin and Rajit Manohar. General Approach to Asynchronous Circuits Simulation Using Synchronous FPGAs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 41(10):3452--3465 (TCAD), October 2022. (pdf); Alex Fallin, Aarti Kothari, Jiayuan He, Christopher Yanez, Keshav Pingali, Rajit Manohar, Martin Burtscher. A Simple, Fast, and GPU-friendly Steiner-Tree Heuristic. IEEE International Parallel and Distributed Processing Symposium Workshops, May 2022. (pdf); Jiayuan He, Udit Agarwal, Yihang Yang, Rajit Manohar, Keshav Pingali. SPRoute 2.0: A detailed routability-driven deterministic parallel global router with soft capacity. 27th Asia and South Pacific Design Automation Conference (ASPDAC), January 2022. (pdf); Jiayuan He, Wenmian Hua, Yi-Shan Lu, Sepideh Maleki, Yihang Yang, Keshav Pingali, and Rajit Manohar. interact: An Interactive Design Environment for Asynchronous Logic. Workshop on Open-Source EDA Technology, International Conference on Computer-Aided Design (WOSET), November 2021. (pdf); Rui Li, Lincoln Berkley, Yihang Yang, and Rajit Manohar. Fluid: An Asynchronous High-level Synthesis Tool for Complex Program Structures. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), September 2021. (abstract, pdf) — Best paper nominee; Samira Ataei, Wenmian Hua, Yihang Yang, Rajit Manohar, Yi-Shan Lu, Jiayuan He, Sepideh Maleki, Keshav Pingali. An Open-Source EDA flow for Asynchronous Logic. IEEE Design & Test (special issue on open-source EDA), April 2021. (abstract, pdf); Ned Bingham and Rajit Manohar. A Systematic Approach for Arbitration Expressions. IEEE Transactions on Circuits and Systems I: Regular Papers, 67:(12):4960--4969 (TCAS), December 2020. (abstract, pdf); Udit Agarwal, Samira Ataei, Jiayuan He, Wenmian Hua, Yi-Shan Lu, Sepideh Maleki, Yihang Yang, Keshav Pingali, Rajit Manohar. A Digital Flow for Asynchronous VLSI Systems: Status Update. Workshop on Open-Source EDA Technology, International Conference on Computer-Aided Design (WOSET), November 2020. (pdf); Jiayuan He, Yihang Yang, Rajit Manohar. A power router for gridded cell placement. Workshop on Open-Source EDA Technology, International Conference on Computer-Aided Design (WOSET), November 2020. (pdf); Yihang Yang, Jiayuan He, Rajit Manohar. Dali: A gridded cell placement flow. IEEE International Conference on Computer-Aided Design (ICCAD), November 2020. (abstract, pdf); Rajit Manohar. Exact Timing Analysis for Asynchronous Circuits with Multiple Periods. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39(10):3134--3138 (TCAD), October 2020. (abstract, pdf); Yi-Shan Lu, Rajit Manohar, Keshav Pingali. Blitz: A Static Timing Analyzer Parallelized Using Operator Formulation. Work-in-progress session, Design Automation Conference, July 2020.; Samira Ataei, Rajit Manohar. Shared staticizer for area-efficient asynchronous circuits. Proceedings of the IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2020. (abstract, pdf); Wenmian Hua, Yi-Shan Lu, Keshav Pingali, Rajit Manohar. Cyclone: a static timing and power analysis engine for asynchronous circuits. Proceedings of the IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2020. (abstract, pdf) — Best paper award; Wenmian Hua, Yi-Shan Lu, Keshav Pingali, Rajit Manohar. Cyclone: a fast static timing analysis engine for asynchronous circuits. ACM Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 2020.; Samira Ataei, Yi-Shan Lu, Jiayuan He, Wenmian Hu, Sepideh Maleki, Yihang Yang, Keshav Pingali, Rajit Manohar. Toward a digital flow for asynchronous VLSI systems. Workshop on Open-Source EDA Technology, International Conference on Computer-Aided Design (WOSET), November 2019. (pdf) — 2nd place, best open-source tool; Samira Ataei, Rajit Manohar. A unified memory compiler for synchronous and asynchronous circuits. Workshop on Open-Source EDA Technology, International Conference on Computer-Aided Design (WOSET), November 2019. (pdf) — 3rd place, best open-source tool; Jiayuan He, Martin Burtscher, Rajit Manohar, Keshav Pingali. SPRoute: A Scalable Parallel Negotiation-based Global Router. International Conference on Computer-Aided Design (ICCAD), November 2019. (abstract, pdf); Jiayuan He, Martin Burtscher, Rajit Manohar, Keshav Pingali. SPRoute: A Scalable Parallel Negotiation-based Global Router. Work-in-progress session, Design Automation Conference, June 2019.; Rajit Manohar and Yoram Moses. Asynchronous Signalling Processes. Proceedings of the IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2019. (abstract, pdf); Samira Ataei and Rajit Manohar. AMC: An Asynchronous Memory Compiler. Proceedings of the IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2019. (abstract, pdf) — Best paper nominee; Nitish Srivastava and Rajit Manohar. Operation Dependent Frequency Scaling Using Desynchronization. IEEE Transactions on VLSI, 27(4):799--809 (TVLSI), April 2019. (abstract, pdf); Yi-Shan Lu, Wenmian Hua, Rajit Manohar, and Keshav Pingali. ParallelClosure: A Parallel Design Optimizer for Timing Closure. ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 2019.; Rajit Manohar. An Open-Source Design Flow for Asynchronous Circuits. Government Microcircuit Applications and Critical Technology Conference, March 2019. (abstract, pdf); Yi-Shan Lu, Samira Ataei, Jiayuan He, Wenmian Hu, Sepideh Maleki, Yihang Yang, Martin Burtscher, Keshav Pingali, Rajit Manohar. Parallel Tools for Asynchronous VLSI Systems. Workshop on Open-Source EDA Technology, International Conference on Computer-Aided Design (WOSET), November 2018. (abstract, pdf); Wenmian Hua and Rajit Manohar. Exact Timing Analysis for Asynchronous Systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37(1):203-216 (TCAD), January 2018. (abstract, pdf); Asa Dan, Rajit Manohar, and Yoram Moses. On Using Time Without Clocks via Zigzag Causality. ACM Symposium on Principles of Distributed Computing (PODC), July 2017. (abstract, pdf); Rajit Manohar and Yoram Moses. The Eventual C-Element Theorem for Delay-Insensitive Asynchronous Circuits. Proceedings of the IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2017. (abstract, pdf) — Best paper nominee; Nitish Srivastava, Steve Dai, Rajit Manohar, and Zhiru Zhang. Accelerating Face Detection on Programmable SoC Using C-Based Synthesis. Proc. ACM Symposium on Field-Programmable Gate Arrays (FPGA), February 2017. (abstract, pdf); Filipp Akopyan, Carlos Tadeo Ortega Otero, and Rajit Manohar. Hybrid Synchronous-Asynchronous Tool Flow for Emerging VLSI Design. IEEE International Workshop on Logic Synthesis (IWLS), June 2016. (abstract, pdf); Wenmian Hua and Rajit Manohar. Exact Timing Analysis for Concurrent Systems. Work-in-progress session, Design Automation Conference, June 2016.; Sandra Jackson and Rajit Manohar. Gradual Synchronization. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2016. (abstract, pdf) — Best paper nominee; Stephen Longfield, Brittany Nkounkou, Rajit Manohar, and Ross Tate. Preventing Glitches and Short Circuits in High-Level Self-Timed Chip Specifications. 36th Annual ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), June 2015. (abstract, pdf); Rajit Manohar and Yoram Moses. Analyzing Isochronic Forks with Potential Causality. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2015. (abstract, pdf) — Best paper nominee; Robert Karmazin, Stephen Longfield, Carlos Tadeo Ortega Otero, and Rajit Manohar. Timing Driven Placement for Quasi Delay-Insensitive Circuits. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2015. (abstract, pdf); Carlos Tadeo Ortega Otero, Jonathan Tse, Robert Karmazin, Benjamin Hill, and Rajit Manohar. Automatic Obfuscated Cell Layout for Trusted Split-Foundry Design. IEEE International Symposium on Hardware-Oriented Security and Trust, May 2015.; Stephen Longfield and Rajit Manohar. Removing Concurrency for Rapid Functional Verification. Proceedings of the 2014 International Conference on Computer-Aided Design (ICCAD), November 2014. (abstract, pdf); Benjamin Hill, Robert Karmazin, Carlos Tadeo Ortega Otero, Jonathan Tse, and Rajit Manohar. A Split-Foundry Asynchronous FPGA. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), September 2013. (abstract, pdf); Robert Karmazin, Carlos Otero, and Rajit Manohar. CellTK: Automated Layout for Asynchronous Circuits with Nonstandard Cells. Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2013. (abstract, pdf); Stephen Longfield and Rajit Manohar. Inverting Martin Synthesis for Verification. Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2013. (abstract, pdf) — Best paper award; Christopher LaFrieda and Rajit Manohar. Reducing Power Consumption with Relaxed Quasi Delay-Insensitive Circuits. Proceedings of the 15th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2009. (abstract, pdf); Song Peng, David Fang, John Teifel, and Rajit Manohar. Automated Synthesis for Asynchronous FPGAs. 13th ACM International Symposium on Field Programmable Gate Arrays (FPGA), February 2005. (abstract, pdf, ps); John Teifel and Rajit Manohar. Static Tokens: Using Dataflow to Automate Concurrent Pipeline Synthesis. Proceedings of the 10th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), April 2004. (abstract, pdf, ps); Rajit Manohar. Scalable Formal Design Methods for Asynchronous VLSI. Proceedings of the 29th ACM SIGPLAN/SIGACT Conference on the Principles of Programming Languages [invited] (POPL), Portland, OR, January 2002.; Rajit Manohar. An Analysis of Reshuffled Handshaking Expansions. Proceedings of the 7th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 96--105, Salt Lake City, Utah, March 2001. (abstract, pdf, ps); Rajit Manohar. The Entropy of Traces in Parallel Computation. IEEE Transactions on Information Theory, 45(5):1606--1608, July 1999. (abstract, pdf, ps); Rajit Manohar, Tak-Kwan Lee, and Alain J. Martin. Projection: A Synthesis Technique for Concurrent Systems. Proceedings of the 5th IEEE International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), pp. 125--134, April 1999. (abstract, pdf, ps); K. Rustan M. Leino and Rajit Manohar. Joining Specification Statements. Theoretical Computer Science, 216:375-394, March 1999. (abstract, ps); Rajit Manohar and Alain J. Martin. Slack Elasticity in Concurent Computing . Proceedings of the Fourth International Conference on the Mathematics of Program Construction (MPC), Lecture Notes in Computer Science 1422, pp. 272-285, Springer-Verlag 1998. (abstract, pdf, ps); Donald Dabdub and Rajit Manohar. Performance and Portability of an Air Quality Model. Parallel Computing, special issue on Regional Weather Models, 23(14):2187--2200, 1997. (abstract, ps); José A. Tierno, Rajit Manohar, and Alain J. Martin. The Energy and Entropy of VLSI Computations. Proceedings of the 2nd IEEE International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), pp. 188--196, March 1996. (abstract, pdf, ps); Rajit Manohar and Alain J. Martin. Quasi-delay-insensitive circuits are Turing-complete. Proceedings of the 2nd IEEE International Symposium on Advanced Research in Asynchronous Circuits and Systems [invited] (ASYNC), March 1996. Available as Caltech technical report CS-TR-95-11, November 1995. (abstract, pdf, ps); Rajit Manohar and K. Rustan M. Leino. Conditional Composition. Formal Aspects of Computing, 7(6):683--703, 1995. (abstract, ps); K. Mani Chandy, Rajit Manohar, Berna L. Massingill, and Daniel I. Meiron. Integrating Task and Data Parallelism with the Group Communication Archetype. Proceedings of the Ninth International Parallel Processing Symposium (IPPS), pp. 724--733, 1995. (abstract, ps)
Energy-efficient VLSI [click to toggle all]: Raghavendra Pothukuchi, Karthik Sriram, Michal Gerasimiuk, Muhammed Ugur, Rajit Manohar, Anurag Khandelwal, and Abhishek Bhattacharjee. Distributed Brain-Computer Interfacing with a Networked Multi-Accelerator Architecture. IEEE Micro (special issue on Top Picks from Computer Architecture conferences), 2024. (abstract, pdf); Venkata Pavan Sumanth Sikhakollu, Shreesha Sreedhara, Rajit Manohar, Alan Mishchenko, and Jaijeet Roychowdhury. High Quality Circuit-based 3-SAT Mappings for Oscillator Ising Machines. International Conference on Unconventional Computation and Natural Computation, June 2024. (abstract, pdf); Mattia Vezzoli, Lukas Nel, Kshitij Bhardwaj, Rajit Manohar, and Maya Gokhale. Designing an energy-efficient fully-asynchronous deep learning convolution engine. Late breaking results, Design Automation and Test in Europe (DATE), 2024. (abstract, pdf); Xiaoxuan Yang, Zhangyang Wang, X. Sharon Hu, Chris Kim, Shimeng Yu, Miroslav Pajic, Rajit Manohar, Yiran Chen, and Hai Helen Li. Neuro-symbolic computing: advancements and challenges in hardware-software co-design. IEEE Transactions on Circuits and Systems II (TCAS II), 2023. (abstract, pdf); Noa Zilberman, Eve M. Schooler, Uri Cummings, Rajit Manohar, Dawn Nafus, Robert Soulé, and Rick Taylor. Toward Carbon-Aware Networking. ACM SIGENERGY Energy Informatics Review (EIR), October 2023. (abstract, pdf); Eve Schooler, Rick Taylor, Noa Zilberman, Robert Soulé, Dawn Nafus, Rajit Manohar, and Uri Cummings. A Perspective on Carbon-aware Networking. Internet Architecture Board Workshop on Environmental Impact of Internet Applications and Systems, December 2022. (pdf); Noa Zilberman, Eve M. Schooler, Uri Cummings, Rajit Manohar, Dawn Nafus, Robert Soulé, Rick Taylor. Toward Carbon-Aware Networking. HotCarbon 2022: 1st Workshop on Sustainable Computer Systems Design and Implementation, July 2022. (pdf); Ned Bingham, Rajit Manohar. Self-Timed Adaptive Digit-Serial Addition. IEEE Transactions on VLSI, 27(9):2131--2141 (TVLSI), September 2019. (abstract, pdf); Nitish Srivastava and Rajit Manohar. Operation Dependent Frequency Scaling Using Desynchronization. IEEE Transactions on VLSI, 27(4):799--809 (TVLSI), April 2019. (abstract, pdf); Alexander Neckar, Sam Fok, Ben Benjamin, Terrence C. Stewart, Nick N. Oza, Aaron R. Voelker, Chris Eliasmith, Rajit Manohar, Kwabena Boahen. Braindrop: A Mixed-Signal Neuromorphic Architecture with a Dynamical Systems-Based Programming Model. Proceeedings of the IEEE, 107(1):144--164, January 2019. (abstract, pdf); Ned Bingham and Rajit Manohar. QDI Constant Time Counters. IEEE Transactions on VLSI, 27(1):83--91 (TVLSI), January 2019. (abstract, pdf); Nitish Srivastava and Rajit Manohar. Data Dependent Frequency Scaling using Desynchronization. Work-in-progress session, Design Automation Conference, June 2018.; Yu Chen, Xiaoyang Zhang, Yong Lian, Rajit Manohar, Yannis Tsividis. A Continuous-Time Digital IIR Filter with Signal-Derived Timing and Fully Agile Power Consumption. IEEE Journal of Solid-State Circuits, 53(2):418-430 (JSSC), February 2018. (abstract, pdf); Yu Chen, Xiaoyang Zhang, Yong Lian, Rajit Manohar, and Yannis Tsividis. A Continuous-Time Digital IIR Filter with Signal-Derived Timing. 2017 Symposium on VLSI Circuits, June 2017. (abstract, pdf); Yu Chen, Rajit Manohar, and Yannis Tsividis. Design of Tunable Delay Cells. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), May 2017. (abstract, pdf); Tayyar Rzayev, David Albonesi, Rajit Manohar, Francois Guimbretiere, and Jaeyeon Kihm. Toolbox for Exploration of Energy-Efficient Event Processors for Human-Computer Interaction. Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2017. (abstract, pdf); Rajit Manohar. Comparing Stochastic and Deterministic Computing. IEEE Computer Architecture Letters, 14(2):119--122, July 2015. (abstract, pdf) — Best of Computer Architecture Letters; Jonathan Tse, Benjamin Hill, and Rajit Manohar. A Bit of Analysis on Self-Timed Single-Bit On-Chip Links. Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2013. (abstract, pdf); Basit Riaz Sheikh and Rajit Manohar. An Asynchronous Floating-Point Multiplier. Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2012. (abstract, pdf); Basit Riaz Sheikh and Rajit Manohar. Energy-efficient Pipeline Templates for High Performance Asynchronous Circuits. ACM Journal on Emerging Technologies in Computer Systems (special issue on asynchrony in system design), 7(4), December 2011. (abstract, pdf); Basit Riaz Sheikh and Rajit Manohar. An Operand-Optimized Asynchronous IEEE 754 Double-precision floating-point adder. Proceedings of the 16th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2010. (abstract, pdf) — Best paper award; Carlos Tadeo Ortega Otero, Jonathan Tse, and Rajit Manohar. Static Power Reduction Techniques for Asynchronous Circuits. Proceedings of the 16th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2010. (abstract, pdf); Christopher LaFrieda and Rajit Manohar. Reducing Power Consumption with Relaxed Quasi Delay-Insensitive Circuits. Proceedings of the 15th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2009. (abstract, pdf); David Fang, Filipp Akopyan, and Rajit Manohar. Self-Timed Thermally Aware Circuits. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), March 2006. (abstract, pdf); David Fang and Rajit Manohar. Non-Uniform Access Asynchronous Register Files. Proceedings of the 10th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), April 2004. (abstract, pdf, ps); John Teifel and Rajit Manohar. A High Speed Clockless Serial Link Tranceiver. Proceedings of the 9th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 151--161, Vancouver, BC, May 2003. (abstract, pdf, ps); Virantha Ekanayake and Rajit Manohar. Asynchronous DRAM Design and Synthesis. Proceedings of the 9th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 174--183, Vancouver, BC, May 2003. (abstract, pdf, ps); John Teifel, David Fang, David Biermann, Clinton Kelly IV, and Rajit Manohar. Energy-Efficient Pipelines. Proceedings of the 8th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 21--31, Manchester, UK, March 2002. (abstract, ps); Rajit Manohar. Width-Adaptive Data Word Architectures. Proceedings of the 19th Conference on Advanced Research in VLSI (ARVLSI), pp. 112--129, Salt Lake City, Utah, March 2001. (abstract, pdf, ps); Rajit Manohar. The Entropy of Traces in Parallel Computation. IEEE Transactions on Information Theory, 45(5):1606--1608, July 1999. (abstract, pdf, ps); Rajit Manohar and José A. Tierno. Asynchronous Parallel Prefix Computation. IEEE Transactions on Computers, Vol. 47, No. 11, 1244-1252, November 1998. (abstract, ps); José A. Tierno, Rajit Manohar, and Alain J. Martin. The Energy and Entropy of VLSI Computations. Proceedings of the 2nd IEEE International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), pp. 188--196, March 1996. (abstract, pdf, ps)
Asynchronous FPGAs [click to toggle all]: Prafull Purohit and Rajit Manohar. Field-programmable encoding for address-event representation. Frontiers in Neuroscience, 16, December 2022. (pdf); Rashid Kaleem, Rajit Manohar, and Keshav Pingali. Dionysus: CPUs as accelerators for FPGAs. Work-in-progress session, Design Automation Conference, June 2017.; Carlos Tadeo Ortega Otero, Jonathan Tse, Robert Karmazin, Benjamin Hill, and Rajit Manohar. Automatic Obfuscated Cell Layout for Trusted Split-Foundry Design. IEEE International Symposium on Hardware-Oriented Security and Trust, May 2015.; Benjamin Hill, Robert Karmazin, Carlos Tadeo Ortega Otero, Jonathan Tse, and Rajit Manohar. A Split-Foundry Asynchronous FPGA. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), September 2013. (abstract, pdf); Christopher LaFrieda, Benjamin Hill, and Rajit Manohar. An Asynchronous FPGA with Two-Phase Enable-Scaled Routing. Proceedings of the 16th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2010. (abstract, pdf) — Best paper nominee; S. Ramaswamy, L. Rockett, D. Patel, S. Danziger, R. Manohar, C. Kelly, J. Holt, V. Ekanayake, D. Elftmann. A Radiation Hardened Reconfigurable FPGA. Proceedings of the IEEE Aerospace Conference, March 2009. (abstract, pdf); Rajit Manohar, Clinton Kelly IV, et al. Development of Reprogrammable Low Power High Density High Speed RADHARD FPGAs. Government Microcircuit Applications and Critical Technology Conference, March 2007.; Rajit Manohar. Reconfigurable Asynchronous Logic. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), September 2006. (abstract, pdf); David Fang, Christopher LaFrieda, Song Peng, and Rajit Manohar. A 3-Tier Asynchronous FPGA. Proceedings of the 23rd International VLSI/ULSI Multilevel Interconnection Conference (VMIC), September 2006. (abstract, pdf); Rajit Manohar, Clinton Kelly IV, J. Holt, Chris Liu, Leonard Rockett, Dinu Patel, Steven Danzinger. Application of Low Power High Density Gigahertz Speed Commercial FPGA Technology to High Radiation Applications using RADHARD-by-Process Techniques. Proceedings of the 9th Military and Aerospace Programmable Logic Devices International Conference, September 2006.; David Fang, John Teifel, and Rajit Manohar. A High-Performance Asynchronous FPGA: Test Results. 2005 IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), April 2005. (abstract, pdf); Song Peng, David Fang, John Teifel, and Rajit Manohar. Automated Synthesis for Asynchronous FPGAs. 13th ACM International Symposium on Field Programmable Gate Arrays (FPGA), February 2005. (abstract, pdf, ps); John Teifel and Rajit Manohar. An Asynchronous Dataflow FPGA Architecture. IEEE Transactions on Computers (special issue on field-programmable logic), November 2004. (abstract, pdf); John Teifel and Rajit Manohar. Static Tokens: Using Dataflow to Automate Concurrent Pipeline Synthesis. Proceedings of the 10th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), April 2004. (abstract, pdf, ps); John Teifel and Rajit Manohar. Highly Pipelined Asynchronous FPGAs. 12th ACM International Symposium on Field-Programmable Gate Arrays (FPGA), Monterey, CA, February 2004. [Please see abstract]. (abstract, pdf, ps); John Teifel and Rajit Manohar. Programmable Asynchronous Pipeline Arrays. Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL), pp. 345--354, Lisbon, Portugal, September 2003. (abstract, pdf, ps)
Ultra Low Power Embedded Systems [click to toggle all]: Venkata Pavan Sumanth Sikhakollu, Shreesha Sreedhara, Rajit Manohar, Alan Mishchenko, and Jaijeet Roychowdhury. High Quality Circuit-based 3-SAT Mappings for Oscillator Ising Machines. International Conference on Unconventional Computation and Natural Computation, June 2024. (abstract, pdf); Prafull Purohit, Johannes Leugering, and Rajit Manohar. An Efficient Data Structure for Sparse Bit-Vectors with Applications in Neuromorphic Computing. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), July 2023. (abstract, pdf); Karthik Sriram, Raghavendra Pothukuchi, Michal Gerasimuk, Muhammed Ugur, Oliver Ye Rajit Manohar Anurag Khandelwal, and Abhishek Bhattacharjee. SCALO: An Accelerator-Rich Distributed System for Scalable Brain-Computer Interfacing . IEEE/ACM International Symposium on Computer Architecture (ISCA), July 2023. (abstract, pdf) — Best paper award — IEEE Micro Top Picks; Abhishek Bhattacharjee, Rajit Manohar, and Karthik Sriram,. RETROSPECTIVE: Hardware-software co-design for Brain-Computer Interfaces. ISCA@50 Retrospective, June 2023. (pdf) — ISCA-50 25-year retrospective; Karthik Sriram, Ioannis Karageorgos, Xiayuan Wen, Jan Vesely, Nick Lindsay, Michael Wu, Lenny Kazan, Raghavendra Pothukuchi, Rajit Manohar, and Abhishek Bhattacharjee. HALO: A Hardware-Software Co-Designed Processor for Brain-Computer Interfaces. IEEE Micro, Vol. 43, Issue 3, Special issue from the HotChips 2022 conference, 2023. (pdf); Prafull Purohit and Rajit Manohar. Hierarchical Token Rings for Address-Event Encoding. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), September 2021. (abstract, pdf); Karthik Sriram, Ioannis Karageorgos, Jan Vesely, Nick Lindsay, Xiayuan Wen, Michael Wu, Marc Powell, David Borton, Rajit Manohar, Abhishek Bhattacharjee. Balancing Specialized Versus Flexible Computation in Brain-Computer Interfaces. IEEE Micro (special issue on Top Picks from Computer Architecture conferences), 2021. (pdf); Ioannis Karageorgos, Karthik Sriram, Jan Vesely, Michael Wu, Marc Powell, David Borton, Rajit Manohar, and Abhishek Bhattacharjee. Hardware-software co-design for Brain-Computer Interfaces. Proceedings of the IEEE/ACM Symposium on Computer Architecture (ISCA), June 2020. (abstract, pdf) — IEEE Micro Top Picks; Yu Chen, Xiaoyang Zhang, Yong Lian, Rajit Manohar, Yannis Tsividis. A Continuous-Time Digital IIR Filter with Signal-Derived Timing and Fully Agile Power Consumption. IEEE Journal of Solid-State Circuits, 53(2):418-430 (JSSC), February 2018. (abstract, pdf); Yu Chen, Xiaoyang Zhang, Yong Lian, Rajit Manohar, and Yannis Tsividis. A Continuous-Time Digital IIR Filter with Signal-Derived Timing. 2017 Symposium on VLSI Circuits, June 2017. (abstract, pdf); Yu Chen, Rajit Manohar, and Yannis Tsividis. Design of Tunable Delay Cells. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), May 2017. (abstract, pdf); Carlos Tadeo Ortega Otero, Jonathan Tse, and Rajit Manohar. AES Hardware-Software Co-Design in WSN. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2015. (abstract, pdf); Benjamin Tang, Sunil Bhave, and Rajit Manohar. Low Power Asynchronous VLSI with NEM Relays. Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2014. (abstract, pdf) — Best paper nominee; Jaeyeon Kihm, François Guimbretière, Julia Karl, Rajit Manohar. Using Asymmetric Cores to Reduce Power Consumption for Interactive Devices with Bi-Stable Displays. Proceedings of the ACM CHI Conference on Human Factors in Computing Systems (CHI), April 2014. (abstract, pdf); Carlos Tadeo Ortega Otero, Jonathan Tse, Robert Karmazin, Benjamin Hill, Rajit Manohar. ULSNAP: An Ultra-low Power Event-Driven Microcontroller for Sensor Network Nodes. Proceedings of the IEEE International Symposium on Quality Electronic Design, March 2014. (abstract, pdf); François Guimbretière, Shenwei Liu, Han Wang, Rajit Manohar. An Asymmetric Dual-Processor Architecture for Low Power Information Appliances. ACM Transactions on Embedded Computing Systems, 13(4), February 2014. (abstract, pdf); Jonathan Tse, Benjamin Hill, and Rajit Manohar. A Bit of Analysis on Self-Timed Single-Bit On-Chip Links. Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2013. (abstract, pdf); Benjamin Tang, Stephen Longfield, Rajit Manohar, and Sunil Bhave. Low Power ASIC GPS Tracking Loops: Quantifying the Trade-Offs Between Area, Power and Accuracy. Proc. ION GNSS Technical Meeting, September 2012. — Best presentation award; Benjamin Tang, Stephen Longfield, Sunil Bhave, and Rajit Manohar. A Low Power Asynchronous GPS Baseband Processor. Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2012. (abstract, pdf); Carlos Tadeo Ortega Otero, Jonathan Tse, and Rajit Manohar. Static Power Reduction Techniques for Asynchronous Circuits. Proceedings of the 16th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2010. (abstract, pdf); Filipp Akopyan, Rajit Manohar, and A. Apsel. A level-crossing Flash Asynchronous Analog-to-Digital Converter. Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), March 2006. (abstract, pdf) — Best paper award; Yao-Win Hong, Birsen Sirkeci-Mergen, Anna Scaglione, and Rajit Manohar. Dense Sensor Networks are also Energy-efficient: when `more' is `less'. Proceedings of MILCOM 2005, October 2005. (abstract, pdf) — IEEE Fred Ellersick Award for the best unclassified paper at MILCOM; Virantha Ekanayake, Clinton Kelly IV, and Rajit Manohar. An Ultra-low-power Processor for Sensor Networks. Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2004. (abstract, pdf, ps); Clinton Kelly IV, Virantha Ekanayake, and Rajit Manohar. SNAP: A Sensor Network Asynchronous Processor. Proceedings of the 9th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 24--33, Vancouver, BC, May 2003. (abstract, pdf, ps); Rajit Manohar and Anna Scaglione. Power Optimal Routing in Wireless Networks. IEEE International Conference on Communications, pp. 2979--2984, Anchorage, AK, May 2003. (abstract, pdf); José A. Tierno, Rajit Manohar, and Alain J. Martin. The Energy and Entropy of VLSI Computations. Proceedings of the 2nd IEEE International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), pp. 188--196, March 1996. (abstract, pdf, ps)
Asynchronous Computer Architecture [click to toggle all]: Esteban Ramos, Robert Soulé, Peter Alvaro, Pietro Bressana, Edmund Chen, Uri Cummings, Rui Li, James Tsai, and Rajit Manohar. Split gRPC: An Isolation Architecture for RPC Software Stacks. ACM SIGOPS Asia-Pacific Workshop on Systems, July 2024. (abstract, pdf); Raghavendra Pothukuchi, Karthik Sriram, Michal Gerasimiuk, Muhammed Ugur, Rajit Manohar, Anurag Khandelwal, and Abhishek Bhattacharjee. Distributed Brain-Computer Interfacing with a Networked Multi-Accelerator Architecture. IEEE Micro (special issue on Top Picks from Computer Architecture conferences), 2024. (abstract, pdf); Karthik Sriram, Raghavendra Pothukuchi, Michal Gerasimuk, Muhammed Ugur, Oliver Ye Rajit Manohar Anurag Khandelwal, and Abhishek Bhattacharjee. SCALO: An Accelerator-Rich Distributed System for Scalable Brain-Computer Interfacing . IEEE/ACM International Symposium on Computer Architecture (ISCA), July 2023. (abstract, pdf) — Best paper award — IEEE Micro Top Picks; Abhishek Bhattacharjee, Rajit Manohar, and Karthik Sriram,. RETROSPECTIVE: Hardware-software co-design for Brain-Computer Interfaces. ISCA@50 Retrospective, June 2023. (pdf) — ISCA-50 25-year retrospective; Karthik Sriram, Ioannis Karageorgos, Xiayuan Wen, Jan Vesely, Nick Lindsay, Michael Wu, Lenny Kazan, Raghavendra Pothukuchi, Rajit Manohar, and Abhishek Bhattacharjee. HALO: A Hardware-Software Co-Designed Processor for Brain-Computer Interfaces. IEEE Micro, Vol. 43, Issue 3, Special issue from the HotChips 2022 conference, 2023. (pdf); Adam Wolnikowski, Stephen Ibanez, Jonathan Stone, Changhoon Kim, Rajit Manohar, Robert Soulé. Zerializer: Towards Zero-Copy Serialization. 18th Workshop on Hot Topics in Operating Systems (HotOS), May/June 2021. (abstract, pdf); Karthik Sriram, Ioannis Karageorgos, Jan Vesely, Nick Lindsay, Xiayuan Wen, Michael Wu, Marc Powell, David Borton, Rajit Manohar, Abhishek Bhattacharjee. Balancing Specialized Versus Flexible Computation in Brain-Computer Interfaces. IEEE Micro (special issue on Top Picks from Computer Architecture conferences), 2021. (pdf); Ioannis Karageorgos, Karthik Sriram, Jan Vesely, Michael Wu, Marc Powell, David Borton, Rajit Manohar, and Abhishek Bhattacharjee. Hardware-software co-design for Brain-Computer Interfaces. Proceedings of the IEEE/ACM Symposium on Computer Architecture (ISCA), June 2020. (abstract, pdf) — IEEE Micro Top Picks; Ned Bingham, Rajit Manohar. Self-Timed Adaptive Digit-Serial Addition. IEEE Transactions on VLSI, 27(9):2131--2141 (TVLSI), September 2019. (abstract, pdf); Nitish Srivastava and Rajit Manohar. Operation Dependent Frequency Scaling Using Desynchronization. IEEE Transactions on VLSI, 27(4):799--809 (TVLSI), April 2019. (abstract, pdf); Ned Bingham and Rajit Manohar. QDI Constant Time Counters. IEEE Transactions on VLSI, 27(1):83--91 (TVLSI), January 2019. (abstract, pdf); Nitish Srivastava and Rajit Manohar. Data Dependent Frequency Scaling using Desynchronization. Work-in-progress session, Design Automation Conference, June 2018.; Tayyar Rzayev, Saber Moradi, David Albonesi, and Rajit Manohar. DeepRecon: Dynamically Reconfigurable Architecture for Accelerating Deep Neural Networks. Proceedings of the International Joint Conference on Neural Networks (IJCNN), May 2017. (abstract, pdf); Tayyar Rzayev, David Albonesi, Rajit Manohar, Francois Guimbretiere, and Jaeyeon Kihm. Toolbox for Exploration of Energy-Efficient Event Processors for Human-Computer Interaction. Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2017. (abstract, pdf); Sandra Jackson and Rajit Manohar. Gradual Synchronization. IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2016. (abstract, pdf) — Best paper nominee; Rajit Manohar. Comparing Stochastic and Deterministic Computing. IEEE Computer Architecture Letters, 14(2):119--122, July 2015. (abstract, pdf) — Best of Computer Architecture Letters; Jaeyeon Kihm, François Guimbretière, Julia Karl, Rajit Manohar. Using Asymmetric Cores to Reduce Power Consumption for Interactive Devices with Bi-Stable Displays. Proceedings of the ACM CHI Conference on Human Factors in Computing Systems (CHI), April 2014. (abstract, pdf); Carlos Tadeo Ortega Otero, Jonathan Tse, Robert Karmazin, Benjamin Hill, Rajit Manohar. ULSNAP: An Ultra-low Power Event-Driven Microcontroller for Sensor Network Nodes. Proceedings of the IEEE International Symposium on Quality Electronic Design, March 2014. (abstract, pdf); François Guimbretière, Shenwei Liu, Han Wang, Rajit Manohar. An Asymmetric Dual-Processor Architecture for Low Power Information Appliances. ACM Transactions on Embedded Computing Systems, 13(4), February 2014. (abstract, pdf); Christopher LaFrieda, Engin Ipek, Jose Martinez, and Rajit Manohar. Utilizing dynamically coupled cores to form a resilient chip multiprocessor. Proc. International Conference on Dependable Systems and Networks (DSN), June 2007. (abstract, pdf); Jon Russo, Mohammed Amduka, Keith Pendersen, Richard Lethin, Jonathan Springer, Rajit Manohar, Rami Melhem. Enabling Cognitive Architectures for UAV Mission Planning. Proceedings of the High Performance Embedded Computing Workshop (HPEC), September 2006. (abstract, pdf) — Best paper award; Virantha Ekanayake, Clinton Kelly IV, and Rajit Manohar. BitSNAP: Dynamic Significance Compression for a Low Power Sensor Network Asynchronous Processor. Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), March 2005. (abstract, pdf, ps) — Best paper nominee; Rajit Manohar and K. Mani Chandy. Δ-Dataflow Networks for Event Stream Processing. Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems, November 2004. (abstract, pdf, ps) — Best paper award; Virantha Ekanayake, Clinton Kelly IV, and Rajit Manohar. An Ultra-low-power Processor for Sensor Networks. Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2004. (abstract, pdf, ps); David Biermann, Emin Gun Sirer, and Rajit Manohar. A Rate Matching-based Approach to Dynamic Voltage Scaling. Proceedings of the First Watson Conference on the Interaction between Architecture, Circuits, and Compilers, October 2004. (abstract, pdf, ps); David Fang and Rajit Manohar. Non-Uniform Access Asynchronous Register Files. Proceedings of the 10th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), April 2004. (abstract, pdf, ps); Clinton Kelly IV and Rajit Manohar. An Event-Synchronization Protocol for Parallel Simulation of Large-Scale Wireless Networks. Seventh IEEE International Symposium on Distributed Simulation and Real Time Applications, October 2003. (abstract, pdf, ps); Clinton Kelly IV, Virantha Ekanayake, and Rajit Manohar. SNAP: A Sensor Network Asynchronous Processor. Proceedings of the 9th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 24--33, Vancouver, BC, May 2003. (abstract, pdf, ps); Virantha Ekanayake and Rajit Manohar. Asynchronous DRAM Design and Synthesis. Proceedings of the 9th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 174--183, Vancouver, BC, May 2003. (abstract, pdf, ps); Rajit Manohar and Clinton Kelly IV. Network on a Chip: Modeling Wireless Networks with Asynchronous VLSI. IEEE Communications Magazine, pp. 149--155, November 2001. (abstract, pdf, ps); Rajit Manohar. Width-Adaptive Data Word Architectures. Proceedings of the 19th Conference on Advanced Research in VLSI (ARVLSI), pp. 112--129, Salt Lake City, Utah, March 2001. (abstract, pdf, ps); Rajit Manohar, Mika Nyström, and Alain J. Martin. Precise Exceptions in Asynchronous Processors. Proceedings of the 19th Conference on Advanced Research in VLSI (ARVLSI), pp. 16--28, Salt Lake City, Utah, March 2001. (abstract, pdf, ps); Rajit Manohar. A Case for Asynchronous Computer Architecture. Proceedings of the ISCA Workshop on Complexity-Effective Design, June 2000. (abstract, pdf, ps); Rajit Manohar and Mark Heinrich. A Case For Asynchronous Active Memories. ISCA 2000 Solving the Memory Wall Problem Workshop, June 2000. (abstract, ps); Alain J. Martin, Andrew Lines, Rajit Manohar, Mika Nyström, Paul Penzes, Robert Southworth, Uri V. Cummings, and Tak-Kwan Lee. The Design of an Asynchronous MIPS R3000 microprocessor. Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI), pp. 164--181, September 1997. (abstract, pdf, ps)
Three Dimensional Integration [click to toggle all]: Jonathan Tse, Benjamin Hill, and Rajit Manohar. A Bit of Analysis on Self-Timed Single-Bit On-Chip Links. Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), May 2013. (abstract, pdf); T. Robert Harris, Shivam Priyadarshi, Samson Melamed, Carlos Otero, Rajit Manohar, Steven R. Dooley, Nikhil M. Kriplani, W. Rhett Davis, Paul D. Franzon, and Michael B. Steer. A Transient Electrothermal Analysis of Three-Dimensional Integrated Circuits. IEEE Transactions on Components and Packaging Technologies, 2(4):660–667, April 2012. (abstract); S. Priyadarshi, T. R. Harris, S. Melamed, C. Otero, N. Kriplani, C. E. Christoffersen, R. Manohar, S. R. Dooley, W. R. Davis, P. D. Franzon, and M. B. Steer. Dynamic electrothermal simulation of three dimensional integrated circuits using standard cell macromodels. IET Circuits, Devices, and Systems, 6(1):35–44, January 2012.; Filipp Akopyan, Carlos Tadeo Ortega Otero, David Fang, Sandra Jackson, and Rajit Manohar. Variability in 3-D Integrated Circuits. Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), September 2008. (abstract, pdf); David Fang, Christopher LaFrieda, Song Peng, and Rajit Manohar. A 3-Tier Asynchronous FPGA. Proceedings of the 23rd International VLSI/ULSI Multilevel Interconnection Conference (VMIC), September 2006. (abstract, pdf); Song Peng and Rajit Manohar. Yield Enhancement of Asynchronous Logic Circuits through 3-Dimensional Integration Technology. Proceedings of the ACM Great Lakes Symposium on VLSI (GLVLSI), April 2006. (abstract, pdf); Christianto C. Liu, Jeng-Huei Chen, Rajit Manohar, and Sandip Tiwari. Mapping Multimedia Applications to 3-D System-on-Chip. Proceedings of the 2005 IEEE International Symposium on Circuits and Systems, May 2005.
Resilient Asynchronous Systems [click to toggle all]: S. Ramaswamy, L. Rockett, D. Patel, S. Danziger, R. Manohar, C. Kelly, J. Holt, V. Ekanayake, D. Elftmann. A Radiation Hardened Reconfigurable FPGA. Proceedings of the IEEE Aerospace Conference, March 2009. (abstract, pdf); Christopher LaFrieda, Engin Ipek, Jose Martinez, and Rajit Manohar. Utilizing dynamically coupled cores to form a resilient chip multiprocessor. Proc. International Conference on Dependable Systems and Networks (DSN), June 2007. (abstract, pdf); Rajit Manohar, Clinton Kelly IV, et al. Development of Reprogrammable Low Power High Density High Speed RADHARD FPGAs. Government Microcircuit Applications and Critical Technology Conference, March 2007.; Rajit Manohar, Clinton Kelly IV, J. Holt, Chris Liu, Leonard Rockett, Dinu Patel, Steven Danzinger. Application of Low Power High Density Gigahertz Speed Commercial FPGA Technology to High Radiation Applications using RADHARD-by-Process Techniques. Proceedings of the 9th Military and Aerospace Programmable Logic Devices International Conference, September 2006.; Song Peng and Rajit Manohar. Yield Enhancement of Asynchronous Logic Circuits through 3-Dimensional Integration Technology. Proceedings of the ACM Great Lakes Symposium on VLSI (GLVLSI), April 2006. (abstract, pdf); Song Peng and Rajit Manohar. Self-healing Asynchronous Arrays. Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), March 2006. (abstract, pdf); Song Peng and Rajit Manohar. Efficient Failure Detection in Pipelined Asynchronous Circuits. Proceedings of the IEEE Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), October 2005. (abstract, pdf); Song Peng and Rajit Manohar. Fault Tolerant Asynchronous Adders through Dynamic Self-reconfiguration. Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2005. (abstract, pdf); Christopher LaFrieda and Rajit Manohar. Robust Fault Detection and Isolation Techniques for Quasi Delay-Insensitive Circuits. Proceedings of the International Conference on Dependable Systems and Networks (DSN), July 2004. (abstract, pdf, ps)
Selected Technical Reports:: Rajit Manohar. The Impact of Asynchrony on Computer Architecture. Ph.D. thesis, California Institute of Technology, 1998. Available as Caltech technical report CS-TR-98-12 from the Caltech Computer Science department.; Rajit Manohar and Paolo A.G. Sivilotti. Composing Processes Using Modified Rely-Guarantee Specifications. Caltech technical report CS-TR-96-22, November 1996.; Rajit Manohar. Folded FIFOs. Caltech technical report CS-TR-95-09, July 1995.
Issued Patents:: US Patent and Trademark Office search
Notes:: These are "scraps of paper" that are part of my research notes. Some of them turn into publications, but they all contain some idea that I thought was worth recording at the time. If you are interested in any of them (some of them have been cited by papers), send me e-mail.

Errata:

The paper on "Slack Elasticity" published in the proceedings of the conference on the Mathematics of Program Construction (1998) has an error in the final printed version due to an unfortunate oversight in proof-reading. Corollary 1 should read: If a system satisfies its specification when the slack on channel c is k, and if it is unchanged when the slack on channel c is l (> k), it satisfies its specification when the slack on c is s, for all s satisfying k <= s <= l. An examination of the proof shows that this is the statement being established, so the proof is identical. This statement was the version presented at the conference as well.
The paper on "AMC" published in ASYNC 2019 has an error in Figure 2 in the write completion circuitry. The p-stack should be powered with Vdd, the output is taken from the node between the n-fet and p-fets, and there is an input inverter on the wreq line. (Thanks to Matt Guthaus for pointing this out!)
The paper on "The impact of on-chip communication on memory technologies for neuromorphic systems" (and the equation replicated in the CICC overview) presents a simple model of spike queuing delay where the number of spikes is NR/2; this examines spikes generated in one second, and can be too conservative. Instead, one should select a time window dT where the queuing effect is considered, and the spike count would be NR*dT/2. This can change the absolute bandwidth required, depending on the choice of dT. dT has to determined by the worst-case spike queuing scenario for the architecture, and can reduce the bandwidth requirements by 10-100x. (Thanks to Bryce Primavera from NIST for requesting a clarification on the analysis.)

Publications

Selected Technical Reports:

Issued Patents:

Notes: